Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S708000, C257S731000, C257S732000, C257S688000, C257S689000, C257S707000

Reexamination Certificate

active

06853066

ABSTRACT:
A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7and8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7and8) and the mounting substrate, thereby raising the reliability of the soldering connection.

REFERENCES:
patent: 5311402 (1994-05-01), Kobayashi et al.
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5699610 (1997-12-01), Shimada et al.
patent: 6205026 (2001-03-01), Wong et al.
patent: 6246583 (2001-06-01), Cronin et al.
patent: 6392888 (2002-05-01), Chen et al.
patent: 6515861 (2003-02-01), Andric et al.
patent: 6519154 (2003-02-01), Chiu
patent: 6791184 (2004-09-01), Deeney et al.
patent: 20040021216 (2004-02-01), Hosoya
U.S. patent application Ser. No. 10/613,903, Hosoya, filed Feb. 5, 2004.

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