Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-04-26

2005-04-26

Tran, M. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

06885572

ABSTRACT:
There is provided a semiconductor memory device including: a memory cell array; a plurality of sub-banks having a plurality of main amplifiers being placed to the memory cell array and being used to amplify data read from the memory cell array; a plurality of data inputting and outputting pads arranged in a wiring space placed among the sub-banks; a plurality of global input and output lines to connect the main amplifiers and the data inputting and outputting pads; and wherein the sub-banks is divided into a plurality of groups of the sub-banks and the data inputting and outputting pads is divided in a manner so as to be corresponded to the plurality of groups of the sub-banks and wherein the main amplifiers belonging to one of the groups of the sub-banks being placed far from a corresponding data inputting and outputting pads is arranged in same order as the corresponding data inputting and outputting pads, and the main amplifiers belonging to an other of the groups of the sub-banks being placed near to a corresponding data inputting and outputting pads is arranged in order symmetric to an order in which the corresponding data inputting and outputting pads is arranged and wherein its wiring is carried out so that the global input and output lines is placed in a distributed manner without being concentrated in certain places in each of the groups of the sub-banks.

REFERENCES:
patent: 6163475 (2000-12-01), Proebsting
patent: 6310815 (2001-10-01), Yamagata et al.

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