Content addressable memory having dynamic match resolution

Details Content addressable memory having dynamic match resolution Content addressable memory having dynamic match resolution

2005-05-24

2005-05-24

Lam, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C711S108000

Reexamination Certificate

active

06898099

ABSTRACT:
A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

REFERENCES:
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IBM Technical Disclosure Bulletin, “Self-Timed Hit Circuit for a Content Addressable Memory,” vol. 38, No. 2, Feb. 1995, pp. 65-66 plus cover and end page; total 4 pages.

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