Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-09-06
2005-09-06
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S191000
Reexamination Certificate
active
06940782
ABSTRACT:
A memory system and a control method for the same enable stable operation at high frequencies without a radiant noise problem. In the memory system, a plurality of DRAMs is provided on each of a plurality of modules, and each DRAM is connected with a memory controller by data lines and clock lines. The clock lines have a topology exclusively applied to each module, while the data lines have a topology for connecting them to their associated DRAMs on each module. Command/address lines also have a topology similar to that of the clock lines. In this case, data signals supplied through the data lines and clock and command/address signals supplied through the clock lines and the command/address lines are transferred at different timings between the DRAMs and the memory controller. For this reason, the DRAMs and the memory controller are provided with circuits for matching the timings.
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Japanese translation of Korean Office action prepared by Korean associate and sent to Japanese associate on May 9, 2005.
Untranslated Korean Office Action issued on Apr. 29, 2005 in connection with corresponding Korean application No. 10-2003-0037836.
English translation of relevant portions of Korean Patent Office Action issued Apr. 29, 2005 submitted in lieu of statement of relevancy of prior art teachings to the instant application.
Elpida Memory Inc.
Ostrolenk Faber Gerb & Soffen, LLP
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