Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185210, C365S185220, C365S185030, C365S185280

Reexamination Certificate

active

06839279

ABSTRACT:
A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

REFERENCES:
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 6501674 (2002-12-01), Ashikaga
patent: 6639849 (2003-10-01), Takahashi et al.

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