Phase comparator circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Reexamination Certificate

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Details

C327S002000

Reexamination Certificate

active

06888379

ABSTRACT:
A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal3of a multiplier circuit62approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

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patent: 5661419 (1997-08-01), Bhagwan
patent: 6157686 (2000-12-01), Iinuma
patent: 6493163 (2002-12-01), Reed et al.
patent: 6-252654 (1994-09-01), None
Ishihara, N., “A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample-and-Hold Technique”, IEEE J. Solid State Circuits, vol. SC-29, pp. 1566-1571, Dec. 1994.
Hogge, JR., C., “A Self Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, vol. LT-3, No. 6, pp. 1312-1314, Dec. 1985.

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