Semiconductor package free of substrate and fabrication...

Details Semiconductor package free of substrate and fabrication... Semiconductor package free of substrate and fabrication...

2005-04-26

2005-04-26

Guerrero, Maria F. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C438S108000, C438S127000, C438S612000, C438S613000, C438S614000, C438S687000

Reexamination Certificate

active

06884652

ABSTRACT:
A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

REFERENCES:
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patent: 5859475 (1999-01-01), Freyman et al.
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patent: 6130115 (2000-10-01), Okumura et al.
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patent: 6229200 (2001-05-01), McLellan et al.
patent: 6372540 (2002-04-01), Huemoeller
patent: 6514847 (2003-02-01), Ohsawa et al.
patent: 6578754 (2003-06-01), Tung

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