Integrated circuit with modified metal features and method...

Details Integrated circuit with modified metal features and method... Integrated circuit with modified metal features and method...

Filed on

2005-04-12

Date issued

2005-04-12

Examiner

Nelms, David (Department: 2818)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Combined with electrical contact or lead

SubSubClass

Of specified material other than unalloyed aluminum

Type

Reexamination Certificate

Status

active

Patent number

06879045

Description

ABSTRACT:
Embodiments of the invention concern modifying the layout of one or more metal layers of an integrated circuit before patterning those layers, so that an intermetal dielectric layer (IDL) subsequently deposited over the top surface of the patterned layer will be substantially self-planarized. The spacing between parallel edges of adjacent first metal lines and features is standardized, and one or more additional metal features are included in areas where an intersection exists. The additional metal features serve to maintain the elevation of the top surface of the IDL at the same height across the intersections, thus achieving self-planarization across the entire top surface of the IDL, without the need for a thicker than desired IDL. The modified metal layers are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

REFERENCES:
patent: 5965940 (1999-10-01), Juengling
patent: 5981384 (1999-11-01), Juengling
patent: 6627549 (2003-09-01), Juengling
patent: 6638867 (2003-10-01), Liu et al.

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