Delay lock loop using shift register with token bit to...

Details Delay lock loop using shift register with token bit to... Delay lock loop using shift register with token bit to...

2005-01-25

2005-01-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S163000, C377S069000

Reexamination Certificate

active

06847241

ABSTRACT:
Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.

REFERENCES:
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5870445 (1999-02-01), Farwell
patent: 6333959 (2001-12-01), Lai et al.
patent: 6628154 (2003-09-01), Fiscus
patent: 6639442 (2003-10-01), Ghameshlu et al.

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