Non-volatile semiconductor memory device with reduced chip...

Details Non-volatile semiconductor memory device with reduced chip... Non-volatile semiconductor memory device with reduced chip...

2005-01-04

2005-01-04

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185120, C365S185130, C365S185110, C365S185280, C365S051000, C365S072000

Reexamination Certificate

active

06839283

ABSTRACT:
A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of the plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to the plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among the plurality of word lines and the plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to the arbitrary word line, and residual word lines other than said arbitrary word line and the secondary adjacent word lines, and wherein among the plurality of transfer transistors, transfer transistors for the residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for the arbitrary word line.

REFERENCES:
patent: 4347588 (1982-08-01), Hoffmann et al.
patent: 5619460 (1997-04-01), Kirihata et al.
patent: 6507508 (2003-01-01), Hosono et al.
patent: 2002-141477 (2002-05-01), None

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