Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185220

Reexamination Certificate

active

06891757

ABSTRACT:
A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are connected to word lines, a first voltage generating circuit which generates a first voltage, a second voltage generating circuit which generates a second voltage using the first voltage, a word line selecting circuit which selects at least one of the word lines, a word line voltage supplying circuit which supplies the second voltage to the selected word line through the word line selecting circuit, and a transfer voltage supplying circuit which supplies the first voltage to the word line selecting circuit and stops supplying it to be in a floating state before transferring the second voltage from the word line voltage supplying circuit to the selected word line, in an operation in which the second voltage is supplied to the selected word line after the first voltage is supplied to the word line selecting circuit.

REFERENCES:
patent: 5991201 (1999-11-01), Kuo et al.
patent: 6097630 (2000-08-01), Kobatake
patent: 20010054737 (2001-12-01), Nakamura et al.
patent: 2000-285690 (2000-10-01), None

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