Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2005-03-01
2005-03-01
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S780000, C257S782000, C257S783000, C257S786000, C257S701000, C257S729000, C257S632000, C257S642000
Reexamination Certificate
active
06861763
ABSTRACT:
A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the active surface of the substrate which includes one or more flip-chip dice. In addition, the invention encompasses forming a similar layer on a second substrate to be joined to the first substrate. Contact pads of the second substrate are exposed through the layer thereon to facilitate joining of the two substrates. Semiconductor devices formed by the method are also disclosed.
REFERENCES:
patent: 4273859 (1981-06-01), Mones et al.
patent: 5173220 (1992-12-01), Reiff et al.
patent: 5264061 (1993-11-01), Juskey et al.
patent: 5484314 (1996-01-01), Farnworth
patent: 5705117 (1998-01-01), O'Connor et al.
patent: 5773198 (1998-06-01), Swirbel et al.
patent: 5839722 (1998-11-01), Berlin et al.
patent: 6013419 (2000-01-01), Tani et al.
patent: 6177360 (2001-01-01), Carter et al.
patent: 6197397 (2001-03-01), Sher et al.
patent: 6200646 (2001-03-01), Neckers et al.
patent: 6203885 (2001-03-01), Sher et al.
patent: 6251488 (2001-06-01), Miller et al.
patent: 6259962 (2001-07-01), Gothait
patent: 6268548 (2001-07-01), Elthon et al.
patent: 6326698 (2001-12-01), Akram
patent: 6337122 (2002-01-01), Grigg et al.
patent: 6391251 (2002-05-01), Keicher et al.
patent: 6432752 (2002-08-01), Farnworth
patent: 6461881 (2002-10-01), Farnworth et al.
patent: 6482576 (2002-11-01), Farnworth et al.
patent: 6489007 (2002-12-01), Grigg et al.
patent: 6506671 (2003-01-01), Grigg
patent: 6514798 (2003-02-01), Farnworth
patent: 6524346 (2003-02-01), Farnworth
patent: 6525408 (2003-02-01), Akram et al.
patent: 6544821 (2003-04-01), Akram
patent: 6544902 (2003-04-01), Farnworth
patent: 6548897 (2003-04-01), Grigg
patent: 6549821 (2003-04-01), Farnworth et al.
patent: 6562278 (2003-05-01), Farnworth et al.
patent: 6569753 (2003-05-01), Akram et al.
patent: 6585927 (2003-07-01), Grigg et al.
patent: 6593171 (2003-07-01), Farnworth
patent: 6630365 (2003-10-01), Farnworth et al.
patent: 6635333 (2003-10-01), Grigg et al.
patent: 6619444 (2003-11-01), Earnworth et al.
patent: 0006052 (1979-12-01), None
patent: 9-17783 (1997-01-01), None
patent: 9-36115 (1997-02-01), None
patent: 9-64537 (1997-03-01), None
U.S. Appl. No. 200/0043711 A1 to Akram et al., dated Apr. 18, 2002.
U.S. Appl. No. 2002/0066966 A1 to Farnworth, dated Jun. 6, 2002.
U.S. Appl. No. 2002/0098623 A1 to Akram, dated Jul. 25, 2002.
U.S. Appl. No. 2002/0105074 A1 to Akram et al., dated Aug. 8, 2002.
U.S. Appl. No. 2002/0171177 A1 to Kritchman et al., dated Nov. 21, 2002.
U.S. Appl. No. 2002/0182782 A1 to Farnworth, dated Dec. 5, 2002.
U.S. Appl. No. 2003/0003180 A1 to Farnworth et al., dated Jan. 2, 2003.
U.S. Appl. No. 2003/0003380 A1 to Faraworth et al., dated Jan. 2, 2003.
U.S. Appl. No. 2003/0003405 A1 to Farnworth et al., dated Jan. 2, 2003.
U.S. Appl. No. 2003/0022462 A1 to Farnworth et al., dated Jan. 30, 2003.
U.S. Appl. No. 2003/0043360 A1 to Farnworth, dated Mar. 6, 2003.
U.S. Appl. No. 2003/0068584 A1 to Farnworth et al., dated Apr. 10, 2003.
U.S. Appl. No. 2003/0072926 A1 to Grigg et al., dated Apr. 17, 2003.
U.S. Appl. No. 2003/0077418 A1 to Grigg et al., dated Apr. 24, 2003.
U.S. Appl. No. 2003/0093173 A1 to Farnworth et al., dated May 15, 2003.
U.S. Appl. No. 2003/0098499 A1 to Akram et al., dated May 29, 2003.
U.S. Appl. No. 2003/0102566 A1 to Farnworth, dated Jun. 5, 2003.
U.S. Appl. No. 2003/0129787 A1 to Farnworth, dated Jul. 10, 2003.
U.S. Appl. No. 2003/0139030 A1 to Grigg, dated Jul. 24, 2003.
U.S. Appl. No. 2003/0151167 A1 to Kritchman et al., dated Aug. 14, 2003.
U.S. Appl. No. 2003/0170921 A1 to Akram, dated Sept. 11, 2003.
U.S. Appl. No. 2003/0173665 A1 to Grigg, dated Sept. 18, 2003.
U.S. Appl. No. 2003/0176016 A1 to Grigg, dated Sept. 18, 2003.
U.S. Appl. No. 2003/0201531 A1 to Farnworth et al., dated Oct. 30, 2003.
U.S. Appl. No. 2003/0203158 A1 to Farnworth et al., dated Oct. 30, 2003.
U.S. Appl. No. 2003/0203612 A1 to Akram et al., dated Oct. 30, 2003.
Miller et al., “Maskless Mesoscale Materials Deposition”, Deposition Technology, Sept. 2001, pp. 20-22.
Miller, “New Laser-Directed Deposition Technology”, Microelectronic Fabrication, Aug. 2001, p. 16.
Webpage, Objet Prototyping the Future, “Objet FullCure700 Series”, 1 page.
Webpage, Objet Prototyping the Future, “How it Works”, 2 pages.
U.S. Appl. No. 09/589,841, filed Jun. 8, 2000, entitled “Sterolithographic Methods for Forming a Protective Layer on a Semiconductor Device Substrate and Substrates Including Protective Layers So Formed”, inventor Farnworth et al.
U.S. Appl. No. 09/590,527, filed Jun. 8, 2000, entitled “Structures for Stabliizing Semiconductor Devices Relative to Test Substrates and Methods for Fabricating the Stabilizers”, inventor Salman Akram.
U.S. Appl. No. 09/590,621, filed Jun. 8, 2000, entitled “Stercolithographic Method and Apparatus for Fabricating Stabilizers for Flip-Chip Type Semiconductor Devices and Resulting Structures”, inventor Arkam et al.
U.S. Appl. No. 09/651,930, filed Aug. 31, 2000, entitled “Semiconductor Device Including Leads in Communication with Contact Pads Thereof and a Stereolithographically Fabricated Package Substantially Encapsulating the Leads and Methods for Fabricating the Same”, inventor Salman Akram.
U.S. Appl. No. 10/201,208, filed Jul. 22,2002, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate, Assemblies Including the Solder Mask, and Methods”, inventor Grigg et al.
U.S. Appl. No. 10/370,755, filed Feb. 20, 2003, entitled “Chip Scale Package Structures and Mcthod of Forming Conductive Bumps Thereon”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/455,091, filed Jun. 5, 2003, entitled “Methods for Stercolithographic Processing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/608,749, filed Jun. 26, 2003, entitled “Methods for Labeling Semiconductor Device Components”, inventor Grigg et al.
U.S. Appl. No. 10/619,918, filed Jul. 15, 2003, entitled “Stereolithographic Methods for Fabricating Hermetic Semiconductor Devices Packages and Semiconductor Devices Including Sterolithographically Fabricated Hermetic Packages”, inventor Warrne M. Farnworth.
U.S. Appl. No. 10/672,098, filed Sep. 26, 2003, entitled “Apparatus and Methods for Use in Stereolithographic Proccessing of Components and Assemblies”, inventor Warren M. Farnworth.
U.S. Appl. No. 10/688,354, filed Oct. 17, 2003, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate and Assemblies including the Solder Mask”, inventor Grigg et al.
U.S. Appl. No. 10/690,417, filed Oct. 20, 2003, entitled “Methods of Coating and Singulating Wafers and Chip-Scale Packages Formed Therefrom”, inventor Farnworth et al.
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