Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2005-01-25
2005-01-25
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C438S618000
Reexamination Certificate
active
06846717
ABSTRACT:
An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (21) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.
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PCT/UW03/07783 PCT International Search Report.
Downey Susan H.
Hall Geoffrey B.
Miller James W.
Coleman W. David
Freescale Semiconductor Inc.
Hill Daniel D.
Nguyen Khiem
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