Fishing – trapping – and vermin destroying
Patent
1996-06-07
1998-01-27
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437919, 148DIG111, H01L 218242
Patent
active
057121826
ABSTRACT:
A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements. The capacitor is completed by forming a dielectric layer over the storage electrode and forming a second conductive layer over the dielectric layer to act as a plate electrode capacitively coupled to the storage electrode through the dielectric layer. Other devices, systems and methods are also disclosed.
REFERENCES:
patent: 4009424 (1977-02-01), Itoh
patent: 4700457 (1987-10-01), Matsukawa
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5045899 (1991-09-01), Arimoto
patent: 5047817 (1991-09-01), Wakamiya et al.
patent: 5068200 (1991-11-01), Kang et al.
patent: 5084405 (1992-01-01), Fazan et al.
patent: 5126916 (1992-06-01), Tseng
patent: 5158905 (1992-10-01), Ahn
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5164881 (1992-11-01), Ahn
patent: 5185284 (1993-02-01), Motonami
patent: 5217914 (1993-06-01), Matsumoto et al.
patent: 5218219 (1993-06-01), Ajika et al.
patent: 5244824 (1993-09-01), Sivan
patent: 5274258 (1993-12-01), Ahn
patent: 5309393 (1994-05-01), Sakata et al.
"3-Dimensional Stacked Capacitor for 16M and 64M DRAMS", Ema et al., International ElectronDevices Meeting, Dec., 1988, pp. 592-595.
"Novel High Density, Stacked Capacitor MOS RAM", Koyanagi et al., International Election Devices Meeting, Dec., 1978, pp. 348-351.
Kaga, et al., Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-M DRAM's, IEEE Transactions On Electron Devices, vo. 38, No. 2, Feb. 1991, pp. 255-261.
Bassuk Lawrence J.
Chaudhari Chandra
Donaldson Richard L.
Texas Instruments Incorporated
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