Shift-register circuit

Details Shift-register circuit Shift-register circuit

2005-04-26

2005-04-26

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

C377S079000, C377S081000

Reexamination Certificate

active

06885723

ABSTRACT:
A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source. The third NMOS transistor includes a fourth gate coupled to the first gate, a fourth drain coupled to the second gate, and a fourth source. The fourth NMOS transistor includes a fifth gate coupled to the first source, a fifth drain coupled to the second source, and a fifth source coupled to the ground voltage level. The fifth NMOS transistor having a sixth gate coupled to the third source, a sixth drain coupled to the fourth source, and a sixth source coupled to the ground voltage level. The first inverter acts as an inverse output terminal and is coupled to the second source for outputting an inverse output signal. The second inverter acts as an output terminal and is coupled to the first inverter for outputting an output signal.

REFERENCES:
patent: 5103116 (1992-04-01), Sivilotti et al.
patent: 5170074 (1992-12-01), Aoki
patent: 5434899 (1995-07-01), Huq et al.

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