Method of making triple polysilicon flash EEPROM arrays having a

Details Method of making triple polysilicon flash EEPROM arrays having a Method of making triple polysilicon flash EEPROM arrays having a

1995-10-31

1998-01-27

Niebling, John

Fishing, trapping, and vermin destroying

437 52, 257320, H01L 218247

Patent

active

057121796

ABSTRACT:
As part of a flash EEPROM array on a semiconductor substrate, erase gates are formed in individual trenches between rows of floating gates. The erase gate is positioned along one sidewall of the trench in a manner to be capacitively coupled with the floating gates of one of the rows adjacent the trench but spaced apart from the floating gates of the other row adjacent the trench. In this way, a separate erase gate is provided for each row of floating gates without increasing the size of the array. The erasure of each row can then be individually controlled. Two self-aligned methods of forming such an array are disclosed. One method involves forming a thick insulating layer along one sidewall of the trench and then filling a remaining space adjacent an opposite trench sidewall with polysilicon material forming an erase gate for the row of floating gates adjacent the other sidewall. A second method involves anisotropically etching a layer of polysilicon that is formed over the array in a manner to conform to the trench sidewalls, thereby separating the polysilicon layer into individual erase gates carried by the trench sidewalls.

REFERENCES:
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5354702 (1994-10-01), Arima et al.
patent: 5534456 (1996-07-01), Yuan et al.

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