Dual port memory buffers and a time slot scheduler for an ATM sp

Details Dual port memory buffers and a time slot scheduler for an ATM sp Dual port memory buffers and a time slot scheduler for an ATM sp

1990-12-10

1992-07-14

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370 941, H04Q 1104

Patent

active

051309750

ABSTRACT:
An asynchronous transfer mode switching network system relays packets stored in packet buffer units to output ports designated by the packets, and a time slot scheduling unit assigns time slots to the packets stored in the packet buffer units upon arrival at the packet buffer units for preventing the packets from collision in a space division switching unit, wherein each of the packet buffer units sequentially writes new packets into respective memory locations but randomly reads out the new packets in the time slots assigned by the time slot scheduling unit so that the throughput of the space division switching unit is improved.

REFERENCES:
patent: 4162375 (1979-07-01), Schlichte
patent: 4320501 (1982-03-01), Le Dieu et al.
patent: 4780870 (1988-10-01), McHarg et al.
patent: 4817083 (1989-03-01), Richards
patent: 5040174 (1991-08-01), Takeuchi et al.
Hitoshi Uematsu, Haruhiko Matsunaga and Hitoshi Obara, "A Cell-Based Cross-Connect Switch for ATM Broad Band Network," Proceedings of the 1989 Singapore International Conference on Networks (Jul. 1989): 371-376.
Hitoshi Obara and Tetsujiro Yasushi, "High Speed Transport Processor for Broad-Band Burst Transport System," Proceedings of the 1988 International Conference on Communications (Jul. 1989): 922-927.

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