Delay locked loop and locking method thereof

Details Delay locked loop and locking method thereof Delay locked loop and locking method thereof

2005-09-13

2005-09-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06943602

ABSTRACT:
The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparator for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing unit for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.

REFERENCES:
patent: 5935257 (1999-08-01), Nishimura
patent: 6212126 (2001-04-01), Sakamoto
patent: 6339533 (2002-01-01), Lee et al.
patent: 6594197 (2003-07-01), Okuda et al.
patent: 6724228 (2004-04-01), Kashiwazaki
patent: 6801472 (2004-10-01), Lee
patent: 6803826 (2004-10-01), Gomm et al.
patent: 6819626 (2004-11-01), Okuda et al.

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