Processor, encoder, decoder, and electronic apparatus

Coded data generation or conversion – Digital code to digital code converters – To or from packed format

Reexamination Certificate

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Details

C341S061000, C341S050000, C341S055000

Reexamination Certificate

active

06844834

ABSTRACT:
The present invention provides a processor including a bit-shift circuit for inputting pieces of data held sequentially in a main register and an auxiliary register, shifting the piece of data bit after bit in accordance with a pointer and a bit count and outputting the shifted data by execution of an unpacking instruction specifying the bit count; a mask circuit for masking data output by the bit-shift circuit in accordance with the pointer and the bit count in the execution of the unpacking instruction; and a pointer-updating circuit for updating the value of the pointer by the bit count in the execution of the unpacking instruction.

REFERENCES:
patent: 4853888 (1989-08-01), Lata et al.
patent: 6133859 (2000-10-01), Deygas et al.
patent: 6144321 (2000-11-01), Deygas et al.
patent: 6388583 (2002-05-01), Long et al.
patent: 6404359 (2002-06-01), Sakai

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