Method of erasing an EEPROM cell utilizing a frequency/time...

Details Method of erasing an EEPROM cell utilizing a frequency/time... Method of erasing an EEPROM cell utilizing a frequency/time...

2005-09-20

2005-09-20

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

06947331

ABSTRACT:
A method is provided for erasing a nonvolatile memory cell that includes a source region, a drain region, a floating gate electrode and a control gate electrode to which an erase signal is applied. In accordance with the method, a source bias voltage is applied to the source region, a drain bias voltage is applied to the drain region, and a frequency/time domain based voltage signal is applied to the control gate electrode of the cell as the erase signal.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 6026014 (2000-02-01), Sato et al.
patent: 6111288 (2000-08-01), Watanabe et al.
patent: 6137723 (2000-10-01), Bergemont et al.

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