Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2005-05-10
2005-05-10
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C438S761000
Reexamination Certificate
active
06891270
ABSTRACT:
A simple technique of forming a low-resistant wire is provided in place of a Damascene method. In a three-layer wire composed of a first layer metal film wire, a second layer metal film wire that has fixed side etching portions, and an insulating film pattern, a low-resistant metal such as copper or silver is deposited in concave regions corresponding to the side etching portions of the second layer metal film wire through electrodeposition by electroplating. The above process is applied to a gate electrode and wire of a semiconductor device to obtain a semiconductor device that has high operation speed.
REFERENCES:
patent: 6359320 (2002-03-01), Yamazaki et al.
patent: 6479900 (2002-11-01), Shinogi et al.
patent: 6509649 (2003-01-01), Sugai
patent: 6515365 (2003-02-01), Higashi et al.
patent: 6573602 (2003-06-01), Seo et al.
patent: 20020063287 (2002-05-01), Yamazaki et al.
patent: 20020070382 (2002-06-01), Yamazaki et al.
patent: 20020079503 (2002-06-01), Yamazaki et al.
Hatano et al., “A Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance,” IEDM 97, pp. 523-526.
Wolf, Stanley,Silicon Processing for the VLSI Era, vol. 2, Process Integration, pp. 256-257.
2.1.1a History and Perspective of Cu Plating for ULSI Metallization, The Latest Development on Copper Wire Technique, pp. 23-28.
2.1.1b Cu Electro Plating and Cu Electroless Plating, The Latest Development on Copper Wire Technique, pp. 29-39.
2.1.1c, Coppper Plating Solution and Additives, The Latest Development on Copper Wire Technique, pp. 40-44.
2.1.1d Electrochemical Deposition Equipment Review, The Latest Development on Copper Wire Technique, pp. 45-53.
2.1.1e Chemistry and Apparatus of Plating Bath, The Latest Development on Copper Wire Technique, pp. 54-58.
Cu Film-Formation by CVD Method Problem Focus Gradually Switch Over From Production Technique to Cost, Semiconductor World, 1997. 12, pp. 176-180.
Cu Film-Formation by Sputtering Improvement of Problem Embedding Property by Directional Sputtering, Semiconductor World, 1997., pp. 186-191.
Copper Plating Interconnection in ULSI Multilevel Interconnection Realization of Trench Metallization of 0.25 μm and Aspect Ratio 4, Semiconductor World, 1997.12, pp. 192-196.
Barrier Materials of Cu Damascene TaN and WN have Average Points,Semiconductor World, 1997.12, pp. 91-96.
Sugawara Akira
Tanaka Nobuhiro
Uehara Ichiro
Clark S. V.
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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