Programmable delay for self-timed-margin

Details Programmable delay for self-timed-margin Programmable delay for self-timed-margin

2005-04-26

2005-04-26

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189020

Reexamination Certificate

active

06885610

ABSTRACT:
A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense amplifier for controlling the timing of when the sense amplifier is enabled in relation to the memory array addressing by generating a plurality of delayed versions of the sense amplifier enable signal and coupling one of the delayed versions of the sense amplifier enable signal to the sense amplifier in response to a control signal. By multiplexing multiple delayed versions of the sense amplifier enable signal under control of programmable delay selection logic, an optional delay is provided to make enable the sense amplifier more quickly or more slowly in reference to a memory array signal, depending upon control signal inputs to the selection logic.

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