Stabilization technique for phase-locked frequency synthesizers

Details Stabilization technique for phase-locked frequency synthesizers Stabilization technique for phase-locked frequency synthesizers

2005-03-08

2005-03-08

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S012000

Reexamination Certificate

active

06864753

ABSTRACT:
A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.

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IBM Technical Disclosure Bulletin, Bol 27, pp. 5407-5409, Feb. 1985.*
Paul V. Brennan, Phase-Locked Loops Principles and Practice, McGraw-Hill, pp. 1-30, 1996.*
Lee, Rai-Cheng, et al., “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” 2001 Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, Jun. 14-16, 2001, pp. 39-42, XP-010551491.
[1] C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788-794, May 2000.
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[3] L. Lin, L. Tee, and P. R. Gray, “A 1.4-GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture,” ISSCC Dig. Tech. Paper, pp. 204-205, and 458, Feb. 2000.

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