Delay apparatus and method

Pulse or digital communications – Synchronizers – Self-synchronizing signal

Reexamination Certificate

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C376S364000

Reexamination Certificate

active

06950486

ABSTRACT:
A delay apparatus delays a rising edge and a falling edge of a digital signal. The delay apparatus includes a first edge detection circuit which detects a first edge or rising edge of the digital signal and generates a detection signal; a set circuit that includes a first counter for generating a count value and clearing the count value in response to the detection signal, wherein the set circuit generates a set signal if the count value reaches the number of the reference clock signals corresponding to the delay period of time; a reset circuit which generates a reset signal if an elapsed period of time since a generation of the set signal equals a period of time the digital signal maintains the second logic level; and an output circuit that outputs a delayed digital signal including edges synchronized with the set signal and the reset signal.

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patent: 6130566 (2000-10-01), Yokomizo
patent: 6218869 (2001-04-01), Hongbin Hao et al.
patent: 6341146 (2002-01-01), Johnson et al.
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patent: 6392641 (2002-05-01), Nishimura et al.
patent: 6404458 (2002-06-01), Kang
patent: 6665359 (2003-12-01), Flake
patent: 61-22441 (1988-09-01), None

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