Inductively coupled electrical connectors

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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Details

C257S684000, C257S724000, C257S777000, C257S778000, C438S106000, C438S107000, C438S108000, C438S109000

Reexamination Certificate

active

06885090

ABSTRACT:
Microelectronic packages include a first microelectronic substrate having a first face and a first AC-coupled interconnect element on the first face. A second microelectronic substrate includes a second face and a second AC-coupled interconnect element on the second face. A buried solder bump extends between the first and second faces, and is at least partially buried beneath the first and/or second faces, to maintain the first and second AC-coupled interconnect elements in closely spaced apart relation. The buried solder bump also may couple DC power between the first and second substrates. Other technologies also may be used to maintain the AC-coupled interconnect elements in closely spaced apart relation and to couple DC power between the substrates. The first and second AC-coupled interconnect elements may be first and second capacitor plates, first and second inductors and/or first and second combined inductive and capacitive elements.

REFERENCES:
patent: 5629838 (1997-05-01), Knight et al.
patent: 6175124 (2001-01-01), Cole et al.
patent: 6362972 (2002-03-01), Panella
patent: 6529385 (2003-03-01), Brady et al.
Sim et al.,A I-Gb/s Bidirectional I/O Buffer Using the Current-Mode Scheme,IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 529-535.
Duewer et al.,MEMS-Based Capacitor Arrays for Programmable Interconnected and RF Applications,IEEE, Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, Mar. 1999, pp. 369-377.
Poulton,Signaling in High-Performance Memory Systems,IEEE ISSCC 1999.
Arabi et al.,Modeling Simulation, and Design Methodology of the Interconnect and Packaging of an Ultra-High Speed Source Synchronous Bus,IEEE, 7thTopical Meeting On Electrical Performance Of Electronic Packaging, 1998, pp. 8-11.
Gabara et al., CapacitiveCoupling and Quantized Feedback Applied to Conventional CMOS Technology,IEEE Journal of Solid-State Circuits, vol. 32, No. 3, Mar. 1997, pp. 419-427.
Salzman et al., CapacitiveCoupling Solves the Known Good Die Problem,Proceedings of the IEEE MCMC, 1994, pp. 95-99.
Annotated copy of U.S. Patent No. 5,629,838 to Knight et al., issued May 13, 1997.

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