Method of controlling insulated gate transistor

Details Method of controlling insulated gate transistor Method of controlling insulated gate transistor

2005-09-27

2005-09-27

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

C257S219000, C257S221000, C257S347000, C257S354000, C438S149000

Reexamination Certificate

active

06949777

ABSTRACT:
An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film. The insulated gate transistor is controlled by injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region, and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.

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Kistler N et al: “Symmetric CMOS in fully-depleted silicon-on-insulator using P<+>-polycrystalline SiGe gate electrodes” Electron Devices Meeting, 1993. Technical Digest., International Washington, DC, USA Dec. 5-8, 1993, New York, NY, USA, IEEE, Dec. 5, 1993, pp. 727-730, XP010118301 ISBN: 0-7803-1450-6 *whole document*.

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