Low leakage CMOS power mux

Details Low leakage CMOS power mux Low leakage CMOS power mux

2005-05-17

2005-05-17

Laxton, Gary L. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C326S081000

Reexamination Certificate

active

06894472

ABSTRACT:
A power supply multiplexing circuit including a first supply voltage input. A first pair of cascoded PMOS transistors are in series with the first supply voltage input. A first native NMOS transistor is in series with the first pair of cascoded PMOS transistors. Also, a second supply voltage input and a second pair of cascoded PMOS transistors are in series with the second supply voltage input; and a second native NMOS transistor in series with the second pair of cascoded PMOS transistors. The gates of the first and second native NMOS transistors are driven by two control signals out of phase with each other, and sources of the first and second native NMOS transistors are connected together to output an output voltage.

REFERENCES:
patent: 6049227 (2000-04-01), Goetting et al.

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