Signal layer interconnect using tapered traces

Details Signal layer interconnect using tapered traces Signal layer interconnect using tapered traces

2005-04-05

2005-04-05

Chambliss, Alonzo (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S776000, C257S786000, C361S774000, C361S802000, C174S261000

Reexamination Certificate

active

06876085

ABSTRACT:
An interconnection device has a substrate that includes a conductive trace having an exposed portion at an edge of the substrate. The exposed portion is tapered toward the edge of the substrate. The exposed portion is provided for direct physical contact with a second conductive trace exposed at an edge of a second substrate. A high frequency direct electrical interconnection is thereby provided that reduces the disadvantageous effects of lateral, longitudinal, and co-planar misalignment between the conductive traces.

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patent: 6444923 (2002-09-01), Iriguchi et al.
patent: 6469255 (2002-10-01), Watanabe et al.
patent: 6700207 (2004-03-01), Pekin et al.

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