Folded BGA package design with shortened communication paths...

Details Folded BGA package design with shortened communication paths... Folded BGA package design with shortened communication paths...

2005-03-22

2005-03-22

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S107000, C257S686000, C257S723000, C365S052000

Reexamination Certificate

active

06869825

ABSTRACT:
A method and apparatus for making a multiply folded BGA package design with shortened communication paths and more electrical routing flexibility. A package apparatus includes a substrate and a first integrated circuit (IC), wherein the first IC is electrically connected to the first face of the substrate, and wherein a first segment and a second segment of the substrate are both folded around the first IC. A second IC is electrically connected to the second face of the substrate, such that the second IC is connected to the first and second folded segments of the substrate abode the first IC.

REFERENCES:
patent: 5448511 (1995-09-01), Paurus et al.
patent: 5646446 (1997-07-01), Nicewarner et al.
patent: 5776797 (1998-07-01), Nicewarner et al.
patent: 6121676 (2000-09-01), Solberg
patent: 6225688 (2001-05-01), Kim et al.
patent: 6376769 (2002-04-01), Chung

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