System for monitoring bit errors

Details System for monitoring bit errors System for monitoring bit errors

1979-11-30

1981-09-22

Smith, Jerry

Excavating

371 22, G06F 1110

Patent

active

042914086

ABSTRACT:
A system for monitoring bit errors in digital differential phase modulation communications, comprising a parity counter for counting "1" pulses among n succesive bits at intervals of n bits (n is a positive integer) in a pulse train and for producing a parity bit. The parity bit is located in each side of a transmitter and a receiver, whereby, the parity bit counted in the receiver and the parity bit transmitted from the transmitter to the receiver are compared with each other.

REFERENCES:
patent: 3159809 (1964-12-01), Fierston et al.
patent: 3278898 (1966-10-01), Rumble
patent: 3914741 (1975-10-01), Bonser et al.

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