Method for determining fault coverage from RTL description

Details Method for determining fault coverage from RTL description Method for determining fault coverage from RTL description

2005-04-05

2005-04-05

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C702S058000, C702S081000, C702S117000, C702S123000, C714S031000, C714S046000, C324S512000, C324S531000, C326S104000, C326S124000

Reexamination Certificate

active

06876934

ABSTRACT:
A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

REFERENCES:
patent: 5568493 (1996-10-01), Morris
patent: 5604895 (1997-02-01), Raimi
patent: 5748497 (1998-05-01), Scott et al.
patent: 6532440 (2003-03-01), Boppana et al.
Ghosh et al., “A Design for Testability Technique for RTL Circuits Using Control/Data Flow Extraction”, Jan. 1996, IEEE, pp. 329-336.*
Mao et al., “Improving Gate Level Fault Coverage by RTL Fault Grading”, Jan. 1996, IEEE, pp. 150-159.

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