Methods and apparatuses for maintaining information stored...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185080, C365S185250

Reexamination Certificate

active

06842375

ABSTRACT:
Various apparatuses and methods in which an integrated circuit includes a non-volatile memory cell and a keep mode circuit. The non-volatile memory cell has a charge storage component. The keep mode circuit has a storage device and a keep mode switch. The storage device receives information stored in the non-volatile memory cell. The keep mode switch connects the storage device to the non-volatile memory cell in order to apply a static bias voltage across the charge storage component to restrict charge-loss to a predetermined level.

REFERENCES:
patent: 4375086 (1983-02-01), Van Velthoven
patent: 4467457 (1984-08-01), Iwahashi et al.
patent: 4672580 (1987-06-01), Yau et al.
patent: 4807188 (1989-02-01), Casagrande
patent: 4884241 (1989-11-01), Tanaka et al.
patent: 4951257 (1990-08-01), Imamiya et al.
patent: 4970691 (1990-11-01), Atsumi et al.
patent: 5251171 (1993-10-01), Yamauchi
patent: 5299162 (1994-03-01), Kim et al.
patent: 5331597 (1994-07-01), Tanaka
patent: 5430670 (1995-07-01), Rosenthal
patent: 5587945 (1996-12-01), Lin et al.
patent: 5638325 (1997-06-01), Hamamoto
patent: 5668752 (1997-09-01), Hashimoto
patent: 5732022 (1998-03-01), Kato et al.
patent: 5742542 (1998-04-01), Lin et al.
patent: 5761121 (1998-06-01), Chang
patent: 5768186 (1998-06-01), Ma
patent: 5781489 (1998-07-01), Okamoto
patent: 5801076 (1998-09-01), Ghneim et al.
patent: 5805013 (1998-09-01), Ghneim et al.
patent: 5808953 (1998-09-01), Kim et al.
patent: 5854114 (1998-12-01), Li et al.
patent: 5885870 (1999-03-01), Maiti et al.
patent: 5942780 (1999-08-01), Barsan et al.
patent: 6018477 (2000-01-01), Wang
patent: 6064105 (2000-05-01), Li et al.
patent: 6069382 (2000-05-01), Rahim
patent: 6084820 (2000-07-01), Raszka
patent: 6094394 (2000-07-01), La Rosa
patent: 6295226 (2001-09-01), Yang
patent: 6324097 (2001-11-01), Chen et al.
patent: 6330186 (2001-12-01), Tanaka
patent: 6331951 (2001-12-01), Bautista, Jr. et al.
patent: 6337808 (2002-01-01), Forbes
patent: RE37593 (2002-03-01), Etoh et al.
patent: 6370061 (2002-04-01), Yachareni et al.
patent: 6407946 (2002-06-01), Maruyama et al.
patent: 6417728 (2002-07-01), Baschirotto et al.
patent: 6445614 (2002-09-01), Tsai et al.
patent: 6473356 (2002-10-01), Raszka
patent: 6674665 (2004-01-01), Mann et al.
patent: 20010028590 (2001-10-01), Ishikawa et al.
McPartland et al., “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161.
Simon J. Lovett, “The Nonvolatile Cell Hidden in Standard CMOS Logic Technologies”, IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 1017-1018.
Ohsaki et al., “A Single Polysilicon wafer EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 29*, No. 3, Mar. 1994, pp. 311-316.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods and apparatuses for maintaining information stored... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatuses for maintaining information stored..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatuses for maintaining information stored... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3389767

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.