Semiconductor memory device having improved data retention

Details Semiconductor memory device having improved data retention Semiconductor memory device having improved data retention

2005-07-05

2005-07-05

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185260

Reexamination Certificate

active

06914825

ABSTRACT:
A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the MOS select transistor. The MOS floating gate transistor comprises a floating gate, a second source doping region electrically connected to the first drain doping region of the MOS select transistor, and a second drain doping region electrically connected to a bit line. The second source doping region and the second drain doping region define a floating gate channel. When the MOS floating gate transistor is programmed via a hot electron injection (HEI) mode, the floating gate is a P+doped floating gate; when the MOS floating gate transistor is programmed via a hot hole injection (HHI) mode, the floating gate is an N+doped floating gate.

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