Semiconductor storage device

Static information storage and retrieval – Powering – Conservation of power

Reexamination Certificate

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C365S229000, C365S222000

Reexamination Certificate

active

06922371

ABSTRACT:
A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit2controls n-channel transistors3C,4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors3C,4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit3and a boost circuit4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit3and the boost circuit4.

REFERENCES:
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patent: 5694365 (1997-12-01), Nakai
patent: 5726946 (1998-03-01), Yamagata et al.
patent: 6483764 (2002-11-01), Chen Hsu et al.
patent: 1 152 431 (2001-11-01), None
patent: 6-208790 (1994-07-01), None
patent: 2000-13215 (2000-01-01), None
patent: 2001-52476 (2001-02-01), None

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