Efficient and accurate sensing circuit and technique for low...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185200

Reexamination Certificate

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06898124

ABSTRACT:
An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.

REFERENCES:
patent: 5422854 (1995-06-01), Hirano et al.
patent: 5805500 (1998-09-01), Campardo et al.
patent: 5886925 (1999-03-01), Campardo et al.
patent: 6128225 (2000-10-01), Campardo et al.
patent: 6324098 (2001-11-01), Condemi et al.

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