Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2005-03-15
2005-03-15
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S678000
Reexamination Certificate
active
06867488
ABSTRACT:
An integrated circuit having signal traces, power traces, and ground traces. The signal traces are disposed on at least one signal distribution layer, and the signal traces on the at least one signal distribution layer are formed at no more than a first thickness. The power traces and ground traces are formed on at least one power ground distribution layer, where the at least one power ground distribution layer is an overlying layer of the integrated circuit relative to the at least one signal distribution layer. The power traces and ground traces on the at least one power ground distribution layer are formed at no less than a second thickness that is greater than the first thickness of the signal traces. In this manner, the signal traces, which can be formed with a relatively thin thickness, can be placed very close together on the signal distribution layers, and have sufficient conductivity for the signals transmitted thereon. At the same time, the power and ground traces, which are typically required to carry a greater current, can be formed with a relatively thick thickness and with wider widths, without taking up precious space on the signal distribution layers. In this manner, the signal traces can be placed closed together, both because they are thinner and because space is not taken by power and ground traces on the same layer, and thus they require less space, and the integrated circuit can be made smaller.
REFERENCES:
patent: 4910581 (1990-03-01), Baird
patent: 6022797 (2000-02-01), Ogasawara et al.
patent: 6111310 (2000-08-01), Schultz
patent: 6198164 (2001-03-01), Choi
patent: 6492205 (2002-12-01), Liu et al.
patent: 6509646 (2003-01-01), Lin et al.
patent: 20020079575 (2002-06-01), Hozoji et al.
patent: 20020102835 (2002-08-01), Stucchi et al.
patent: 20030075357 (2003-04-01), Ho et al.
Wong and How, “Low cost flip chip bumping technologies,” Proceedings of the 1stElectronic Packaging Technology Conference, Oct. 8-10, 1997, IEEE, p. 244-250.
Flynn Nathan J.
LSI Logic Corporation
Luedeka Neely & Graham P.C.
Quinto Kevin
LandOfFree
Thick metal top layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thick metal top layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thick metal top layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3377899