Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-07-19

2005-07-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read only systems

C365S104000

Reexamination Certificate

active

06920058

ABSTRACT:
The present invention prevents a reading operation margin from being decreased due to a current injected into a selected bit line after passing through an unselected bit line in a memory cell array configuration using virtual ground lines. A memory cell array is constituted by being divided into at least subarrays of a plurality of columns and memory cell columns at the both ends of the subarrays are constituted so that second electrodes are not connected each other but they are separated from each other between two memory cells adjacent to each other in the row direction at the both sides of boundaries between the subarrays and respectively connected to an independent bit line or virtual ground line, and one of word lines, one of bit lines, and one of virtual ground lines are selected and one memory cell from which data will be read is selected.

REFERENCES:
patent: 5757709 (1998-05-01), Suminaga et al.
patent: 5892713 (1999-04-01), Jyouno et al.
patent: 6226214 (2001-05-01), Choi
patent: 6473327 (2002-10-01), Ishizuka
patent: 10-11991 (1998-01-01), None

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