High speed DRAM architecture with uniform access latency

Details High speed DRAM architecture with uniform access latency High speed DRAM architecture with uniform access latency

2005-05-10

2005-05-10

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S191000, C365S203000, C365S230030

Reexamination Certificate

active

06891772

ABSTRACT:
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

REFERENCES:
patent: 4658354 (1987-04-01), Nukiyama
patent: 5294842 (1994-03-01), Iknaian et al.
patent: 5402388 (1995-03-01), Wojcicki et al.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5550784 (1996-08-01), Takai
patent: 5579267 (1996-11-01), Koshikawa
patent: 5655105 (1997-08-01), McLaury
patent: 5657285 (1997-08-01), Rao
patent: 5666480 (1997-09-01), Leung et al.
patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5713005 (1998-01-01), Proebsting
patent: 5784705 (1998-07-01), Leung
patent: 5787457 (1998-07-01), Miller et al.
patent: RE35934 (1998-10-01), Takai
patent: 5835443 (1998-11-01), Fujita
patent: 5856940 (1999-01-01), Rao
patent: 6014339 (2000-01-01), Kobayashi et al.
patent: 6067274 (2000-05-01), Yoshimoto
patent: 6078546 (2000-06-01), Lee
patent: 6091629 (2000-07-01), Osada et al.
patent: 6151236 (2000-11-01), Bondurant et al.
patent: 6208563 (2001-03-01), Naritake
patent: 6360294 (2002-03-01), Ferrant et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6539454 (2003-03-01), Mes
patent: 6650573 (2003-11-01), Sunaga et al.
patent: 6711083 (2004-03-01), Demone
patent: 0 280 882 (1988-09-01), None
patent: 0 704 848 (1996-03-01), None
patent: 09091955 (1997-04-01), None
Boemo, Lopez-Buedo and Meneses, “The Wave Pipeline Effect on LUT-based FPGA Architectures”, Ciudad Universitaria, Madrid, Spain.
Mehrdad, Heshami et al., “A 250-MHz Skewed—Clock Pipelined Data Buffer”, IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1, 1996; pp. 376-383.

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