Programming of a memory with discrete charge storage elements

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185230

Reexamination Certificate

active

06898128

ABSTRACT:
A non volatile memory (100) includes an array (102) of transistors (30) having discrete charge storage elements (40). The transistors are programmed by using a two step programming method (60) where a first step (68) is hot carrier injection (HCl) programming with low gate voltages. A second step (78) is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.

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Specification; U.S. Appl. No. 10/280,294, filed Oct. 25, 2002, Craig T. Swift et al.

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