Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure
Reexamination Certificate
2002-09-06
2004-06-22
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Lateral bipolar transistor structure
C257S556000, C257S559000, C257S197000, C257S565000, C257S560000, C257S423000
Reexamination Certificate
active
06753592
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an integrated circuit process for providing a complementary bipolar output stage and more particularly to a process that utilizes a self-aligned poly (polysilicon) emitter and a buried power buss for such a stage.
BACKGROUND OF THE INVENTION
Bipolar Complementary Output Stages (BiCMOS) are used wherever possible in integrated circuits. The main reason being that no power is used unless a signal is present. This is very important in many applications where battery operation is used and power needs to be conserved.
FIG. 1
represents a typical class B stage
10
using complementary outputs
12
with two power supplies
14
and
16
. During positive signals the upper Q
1
transistor
18
conducts and the bottom transistor is off. During negative going signals the lower Q
2
transistor
20
conducts and the upper Q
1
transistor
18
is off. There is some distortion in this circuit due to two main causes:
1. The PNP transistor does not have the gain that the NPN transistor has and for the same level of signal does not have the current output. This is due mainly to the mobility of the NPN transistor being higher than the PNP transistor.
2. During crossover from Q
1
transistor
18
to Q
2
transistor
20
conducting there is no current. This causes crossover distortion.
Accordingly, what is desired is to provide a process which overcomes the above identified problems. The process should be cost effective, easy to implement and compatible with existing processes. The process should be a broad use technology that can be utilized in bipolar, BiCMOS, BCD and other multiple type technologies. The present invention addresses such a need while providing a low temperature solution.
SUMMARY OF THE INVENTION
A dual polysilicon emitter, complementary output is provided which utilizes a self-aligned poly emitter process in conjunction with a buried power buss to provide many advantages. While providing these advantages, the process is a low temperature one that is not complicated. The low temperature process that is provided has some additional advantages. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have. Examples of these advantages include:
1. The bipolar, BCD and BiCMOS processes are essentially the same as the standard bipolar or BiCMOS processes being produced generally throughout the industry up through the deposition of polysilicon except that the isolation masking and diffusion process and the sinker masking and diffusion process steps are eliminated. These eliminated steps represent the longest time, highest temperature, and largest area consuming process steps in standard processing used throughout the industry. Their elimination is therefore a significant saving in the process throughput time and cost of making these devices.
2. The dual polysilicon emitter results in self-aligning structures for the extrinsic and intrinsic base, as well as the emitters.
3. The utilization of 0.5 &mgr;m line resolution or lower is encouraged, allowing the devices to perform at much higher frequencies. However, the process and technology is valid from 0.25 &mgr;m to >2.2 &mgr;m; and in many aspects should be used in 2.0 &mgr;m technologies. The process is ideal for analog functions where high current and high power are required and their related larger structures are required for carrying the higher current and the resulting dissipation of high power.
4. Beyond the dual polysilicon emitter process steps, the process is essentially the same as the conventional process except for the addition of etched slots to provide a buried power buss. This results in interconnect metal that at least doubles the metal thickness while only requiring thin metal interconnects to be etched and results in eliminating masks and process steps in the metalization process.
5. The slots utilized for the buried power buss are oxidized and provide oxide isolation instead of junction isolation, resulting in closer spacing, lower leakage, lower capacitance, higher voltage, lower metal resistance, improved electromigration, improved heat transfer, lower Ron, improved performance and a smaller die.
6. The combined process results in an integrated circuit with improved heat transfer capability over presently used processes.
7. Due to the self-aligned features of the process one is able to control critical dimensions with high precision thus allowing the PNP structure to be ratioed to the NPN structure very accurately and eliminating most of the class B distortion that is due to mismatch on present day structures.
8. The self alignment characteristics provided by the Polysilicon process and the structural advantages of the Buried Power Buss provide very low Ron X Area products. This lowers the power dissipation while allowing the matching of the PNP and NPN transistors to be precise. These combinations reduce the class B distortion of the complementary outputs.
REFERENCES:
patent: 4749661 (1988-06-01), Bower
patent: 6118135 (2000-09-01), Gonzalez et al.
patent: 6566733 (2003-05-01), Husher et al.
Eckert George
Micrel Inc.
Nguyen Joseph
Sawyer Law Group LLC
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