Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-10-26
2004-06-08
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000
Reexamination Certificate
active
06747615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a surface discharge type triode plasma display panel.
2. Description of the Related Art
FIG. 1
shows the structure of a surface discharge type triode plasma display panel
1
.
FIG. 2
shows a discharge cell of the plasma display panel
1
shown in FIG.
1
. Referring to
FIGS. 1 and 2
, address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
, dielectric layers
11
and
15
, Y-electrode lines Y
1
, . . . , Y
n
, X electrode lines X
1
, . . . , X
n
, phosphor layers
16
, partition walls
17
, and a magnesium oxide (MgO) protective layer
12
are provided between front and rear glass substrates
10
and
13
of a general surface discharge plasma display panel
1
.
The address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
are formed on the front surface of the rear glass substrate
13
in a predetermined pattern. The lower dielectric layer
15
is formed on the front surfaces of the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The partition walls
17
are formed on the front surface of the lower dielectric layer
15
to be parallel to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. These partition walls
17
define the discharge areas of respective discharge cells and prevent cross talk between discharge cells. The phosphor layers
16
are deposited between the partition walls
17
.
The X electrode lines X
1
, . . . , X
n
and the Y-electrode lines Y
1
, . . . , Y
n
are formed on the rear surface of the front glass substrate
10
in a predetermined pattern to be orthogonal to the address electrode lines A
R1
, A
G1
, . . . , A
Gm
, A
Bm
. The respective intersections define discharge cells. Each of the X electrode lines X
1
, . . . , X
n
includes a transparent conductive indium tin oxide (ITO) electrode line X
na
(
FIG. 2
) and a metal bus electrode line X
nb
(FIG.
2
). Each of the Y-electrode lines Y
1
, . . . , Y
n
includes an ITO electrode line Y
na
(
FIG. 2
) and a metal bus electrode line Y
nb
(FIG.
2
). The upper dielectric layer
11
is formed on the rear surfaces of the X electrode lines X
1
, . . . , X
n
and the Y-electrode lines Y
1
, . . . , Y
n
. The MgO protective layer
12
protects the panel
1
against a strong electrical field and is deposited on the entire rear surface of the upper dielectric layer
11
. A gas, which is used to from a plasma, is hermetically sealed in a discharge space
14
.
A driving method fundamentally adapted to such a plasma display panel
1
as described above is to sequentially perform an initialization step, an address step, and a display step in a unit sub-field. In the initialization step, residual wall charges in the previous sub-field are erased, and space charges are uniformly generated. In the address step, wall charges are produced at selected discharge cells. In the display step, light is emitted from the discharge cells having the wall charges formed in the address step. In other words, when a current (AC) pulse of a relatively high voltage is alternately applied to all the X electrode lines X
1
, . . . , X
n
and all the Y-electrode lines Y
1
, . . . , Y
n
, surface discharges occur at the discharge cells at which the wall charges are formed. Then, plasma is formed in a gas layer of the discharge space
14
, and the phosphor layers
16
are excited due to radiation of ultraviolet rays from the plasma to generate light. Here, to realize gray scales on the plasma display panel
1
, a time division driving method of dividing a unit display period (i.e., a frame) into sub-fields having different display times is used. For example, to achieve a 256 (2
8
) gray scale level with 8-bit image data, 8 sub-fields are set in each unit display period (i.e., a frame in a progressive driving mode or a field in an interlaced driving mode).
For a method of driving such a plasma display panel, a line duplication method of setting discharge cells with respect to both two X electrode lines adjacent to each Y electrode line has been disclosed such as in Japanese Patent Publication No. 160525). According to this line duplication method, the number of X and Y driving lines can be reduced, but the number of driving devices of X and Y driving circuits cannot be eventually reduced.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an object of the present invention to provide a method of driving a plasma display panel in which a number of driving devices of X and Y driving circuits can be eventually reduced by using an AND-logic driving method and in which a number of X and Y driving lines can be eventually reduced by using a line duplication driving method.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
To achieve the above and other objects, a method of driving a plasma display panel, where the plasma display panel includes front and rear substrates disposed opposite each other, X electrode lines and Y electrode lines arranged in parallel on the front substrate between the front and rear substrates, and address electrode lines disposed on the rear substrate in a direction orthogonal to a direction of the X electrode lines and the Y-electrode lines to define discharge cells at intersections thereof, where the discharge cells include odd and even discharge cells set between each Y electrode line and both adjacent X electrode lines above and below each Y electrode line, the method according to an embodiment of the present invention includes a wiring operation, an odd driving operation, and an even driving operation.
According to an aspect of the invention, in the wiring operation, the X electrode lines are divided into odd X groups and even X groups, the Y electrode lines are divided into Y groups, pairs of X and Y groups including pairs of adjacent X and Y electrode lines, respectively, are separately set, and the X and Y electrode lines are commonly connected to one another in units of the odd X groups, the even X groups, and the Y groups.
According to another aspect of the invention, in the odd driving operation, the Y groups, the X groups, and the address electrode lines in an odd field are driven so that odd discharge cells in a vertical direction are driven.
According to yet another aspect of the invention, in the even driving operation, the Y groups, the X groups, and the address electrode lines in an even field are driven so that even discharge cells in a vertical direction are driven.
In a method of driving a plasma display panel according to another embodiment of the present invention, the discharge cells are set using pairs of the X electrode lines adjacent to each one of the Y electrode lines, where the X electrode lines are divided into odd X groups and even X groups, and interlaced scanning is performed by an odd driving operation and an even driving operation, thereby realizing line duplication driving method.
According to a further aspect of the invention, the Y electrode lines are divided into Y groups, and pairs of the X and Y groups including corresponding pairs of the adjacent X and Y electrode lines, respectively, are separately set, and the odd driving operation and the even driving operation are performed in this structure to realize an AND-logic driving method.
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patent: 6188374 (2001-02-01), Moon
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McGuireWoods LLP
Samsung SDI & Co., Ltd.
Wu Xiao
LandOfFree
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