Optical communications – Multiplex – Broadcast and distribution system
Reexamination Certificate
2000-10-03
2004-11-23
Sedighian, M. R. (Department: 2633)
Optical communications
Multiplex
Broadcast and distribution system
C398S060000, C398S075000, C398S078000, C398S164000, C370S458000, C370S461000, C370S462000, C710S116000, C710S117000, C710S123000, C710S124000
Reexamination Certificate
active
06823140
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to computer buses. More particularly, this invention relates to a computer bus that is implemented with optical fibers to avoid the physical limitations associated with traditional computer bus designs.
BACKGROUND OF THE INVENTION
A computer bus is a communication link used to connect multiple computer subsystems. For example, a computer bus is used to link the memory and processor, and to link the processor with input/output (I/O) devices. Computer buses are traditionally classified as follows: processor-memory buses, I/O buses, or backplane buses. Processor-memory buses are short, generally high speed, and matched to the memory system so as to maximize memory-processor bandwidth. I/O buses, by contrast, can be lengthy, can have many types of devices connected to them, and often have a wide range in the data bandwidth of the devices connected to them. Backplane buses are designed to allow processors, memory, and I/O devices to coexist on a single bus. Backplane buses balance the demands of processor-memory communication with the demands of I/O device-memory communication. Backplane buses received their name from the fact that they are typically built into a computer backplane—the fundamental interconnection structure within the computer chassis. Processor, memory, and I/O boards plug into a backplane and then use the backplane bus to communicate.
Processor-memory buses are often design-specific, wile both I/O buses and backplane buses are frequently standard buses with parameters established by industry standards. The distinction between bus types is becoming increasingly difficult to specify. Thus, the present application generically refers to computer buses to encompass all processor-memory buses, I/O buses, and backplane buses.
The problem with computer buses is that they create a communication bottleneck since all input/output must pass through a single bus. Thus, the bandwidth of the bus limits the throughput of the computer. Physical constraints associated with existing computer buses are beginning to limit the available performance improvements generally available in computers.
The physical operation and constraints of existing computer bus designs are most fully appreciated with reference to FIG.
1
.
FIG. 1
illustrates a computer bus
20
positioned on a backplane
22
. The computer bus
20
is a set of wires, effectively forming a transmission line. A random number of system cards (or cards)
24
A-
24
N are attached to the computer bus
20
. By way of example, the cards
24
may include a video processing card, a memory controller card, an I/O controller card, and a network card. Each card
24
is connected to the computer bus
20
through a connector
26
. Thus, each card
24
is electrically connected to the set of wires forming the computer bus
20
. As a result, one card, say card
24
A, can communicate with another card, say card
24
N, by writing information onto the computer bus
20
. Only one card
24
can write information onto the computer bus
20
at a time, thus a computer bus
20
can generate a performance bottleneck as different cards
24
wait to write information onto the bus
20
.
Another problem associated with a traditional computer bus
20
, as shown in
FIG. 1
, is that its performance is constrained by complicated electrical phenomenon. For example, the connectors
26
effectively divide the bus into transmission line segments, resulting in complicated transmission line effects. Note that the transmission line segments will vary depending upon the number of cards
26
connected to the bus
20
. This periodic loading of the bus
20
makes it difficult to optimize bus performance. In addition, each connector
26
produces a lumped discontinuity with parallel capacitance and series inductance, thereby complicating the electrical characteristics of the bus
20
. Note also that “T-connections” are formed between the wires of a computer bus
20
and the wires to a connector
26
. The T-connections complicate the electrical characteristics of the computer bus
20
.
Each card
24
includes a transceiver circuit
28
connected to a card logic circuit
30
, which performs the functional operations associated with the card
24
. The transceiver circuit
28
is used to read and write information on the bus
20
. That is, the transceiver circuit
28
reads information from the bus
20
, the card logic circuit
30
processes the information, and then the transceiver circuit
28
writes processed information to the bus
20
. Additional electrical complications arise with the transceiver circuits
28
. For example, transmission line segments are formed between each connector
26
and each bus transceiver
28
circuit. In addition, the transceiver circuits
28
present an impedance at their package pins that depends upon the circuit design, the electrical state of the transceiver, and the packaging.
In sum, the computer bus
20
constitutes a transmission line with complicated electrical interactions caused by such factors as transmission line segments and connectors forming lumped discontinuities with parallel capacitance and series inductance. The bus
20
may be terminated with termination resistors (R) to reduce transmission line effects, such as reflections and mismatches. Nevertheless, solutions of this sort do not overcome all transmission line problems associated with a computer bus
20
.
Given these complicated electrical interactions, signals on the bus
20
do not experience a uniform rise. That is, if the bus
20
was a perfect transmission line, then high signals (digital ONES) written to the bus
20
would experience a uniform rise. However, in view of the complicated electrical interactions on the bus
20
, high signals frequently experience one or more spurious signal transitions before reaching a final peak value that can be processed. Waiting for signals to settle causes delays. Another problem is that the complicated electrical interactions on the computer bus
20
require higher powered drive signals, and thus more power dissipation.
It is difficult to avoid these problems by changing the electrical characteristics of the bus
20
. That is, it is difficult to design a bus with improved transmission line properties in view of the complicated factors that establish bus
20
performance. Thus, it would be highly desirable to design a new type of bus whose performance is not contingent upon complicated transmission line effects associated with prior art buses.
SUMMARY OF THE INVENTION
An embodiment of the invention includes a set of optical fibers configured to form an optical computer bus between a set of computer sub-system elements of a computer. A set of input optical connector cards are connected to the set of optical fibers. Each of the input optical connector cards includes a transmitting dynamic bandwidth allocator responsive to an optical bus clock signal operating at a multiple of a computer system clock signal such that a set of bus time slots are available for each computer system clock signal cycle. The transmitting dynamic bandwidth allocator allows a light signal to be applied to the optical computer bus during a dynamically assigned bus time slot. In this way, the optical computer bus bandwidth can be dynamically allocated to different computer sub-system elements during a single computer system clock signal cycle.
The optical computer bus is extremely fast, with bus signals moving at approximately the speed of light ((index of refraction of the fiber)
31 1
×the speed of light). The operation of the bus is not compromised by transmission line effects associated with prior art computer buses. Further, the optical computer bus of the invention does not suffer from electrical noise problems. The optical computer bus is compact and is therefore ideal for space-constrained modern computers. Despite its radically different design and configuration, the computer bus of the invention otherwise operates in a standard manner. Thus, the computer bus can be used in
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sedighian M. R.
Sun Microsystems Inc.
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