Real time clock with a power saving counter for embedded...

Details Real time clock with a power saving counter for embedded... Real time clock with a power saving counter for embedded...

2002-12-25

2004-06-29

Wambach, Margaret (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Counter includes circuit for performing an arithmetic function

C377S106000, C377S107000, C327S297000

Reexamination Certificate

active

06757352

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a real time clock for embedded systems. More specifically, a real time clock with a power saving counter for embedded systems is disclosed.
2. Description of the Prior Art
FIG. 1
is a block diagram of a bus clock and a 1 Hz. clock domain in an embedded system
10
. The bus clock domain operates to control the normal functioning of the embedded system by regulating the transfer rates of data. The 1 Hz. domain clock functions as a long-term timer to control the timing of certain events and can issue an interrupt signal based on the value held within the counter block.
The counter block, also called a register block, typically is a set of bit registers within the domain of the 1 Hz. domain clock that keep track of how many seconds have elapsed since the most recent reset. The counter block conventionally receives a signal supplied by an external 1 Hz. clock and additionally has an input for a reset signal RTC_RSTn.
FIG. 2
is a diagram of prior art counter block
20
of a 1 Hz. clock domain in an embedded system. The counter block
20
comprises 32 bit registers REG
0
through REG
31
and 32 half adders HA
0
through HA
31
, each half adder uniquely corresponding with one bit register. Each of the bit registers REG
0
through REG
31
stores a single binary digit of “1” or “0”. Each of the half adders HA
0
through HA
31
is capable of adding two binary digits and outputting a binary sum term and a binary carry term.
For example, if the digits “1” and “1” are added in a half adder, the binary sum term is equal to “0” and the binary carry term is equal to “1”. To facilitate written discussion, in this paper, the bit registers and the half adders will be referenced as if in an array. For example, the REG
0
will be referenced as REG[
0
] although the physical makeup of the counter block
20
is not necessarily so.
Each bit register REG[N] comprises a first input for receiving a signal from a 1 Hz. clock, a second input for receiving a binary sum term outputted from the half adder HA[N], and an output for outputting the value of the bit register REG[N] to the corresponding half adder HA[N]. Each half adder HA[N] comprises a first input for receiving the value of the corresponding bit register REG[N], a second input for receiving a binary carry term from the previous half adder HA[N−1], a first output for outputting the binary sum term to the bit register REG[N], and a second output for outputting the binary carry term to the next half adder HA[N+1]. Because the counter block
20
is used to count elapsed seconds, the value of “1” (for 1 second) is inputted into the second input of the half adder HA[
0
] at the start of each cycle of the 1 Hz. clock.
The counter block
20
operates as follows. Assume that the values in the bit registers REG[
0
] through REG[
31
] are all “0”. When a rising edge of the 1 Hz clock indicates that one second has elapsed, each bit register REG[N] latches the value supplied at the second input of the bit register REG[N]. In this case, the bit register REG[
0
] latches the value of “1” (supplied by the “1” inputted to the second input of the half adder HA[
0
]) and the remaining bit registers REG[
1
] through REG[
31
] latch a “0”.
Then, the half adder HA[
0
] receives the binary digit “1” from the bit register REG[
0
] and the value “1”. After performing the addition, the half adder HA[
0
] outputs the binary sum term “0” to the second input of the REG[
0
] and outputs the carry term “1” to the half adder HA[
1
]. The half adder HA[
1
]) adds the inputted carry term “1” and the “0” outputted from the bit register REG[
1
]. The addition results in a binary sum term “1” being output to the second input of the bit register REG[
1
] and a binary carry term of “0” being transmitted on to the half adder HA[
2
]. The propagation continues sequentially from one bit register REG[N] and half adder HA[N]pair to the next throughout all 32 pairs.
One second later, the 1 Hz. clock triggers another propagation. First, the rising edge of the 1 Hz. clock causes all of the bit registers REG[
0
] through REG[
31
] to latch the value at the second input. In this case, the bit register REG[
1
] will latch a “1” and all of the other bit registers REG[
0
] through REG[
31
] will latch a “0”. The half adder HA [
0
] receives the binary digit “0” from the bit register REG[
0
] and the value “1”. After performing the addition, the half adder HA[
0
] outputs the binary sum term “1” to be stored in the REG[
0
] and outputs the carry term “0” to the half adder HA[
1
]. The half adder HA[
1
] adds the inputted carry term “0” and the “1” inputted from the bit register REG[
1
], transmits the binary sum term “1” back to the second input of the bit register REG[
1
], and transmits the binary carry term “0” on to the half adder HA[
3
] and via propagation throughout the control block
20
.
One skilled in the art will quickly notice that all 32 bit registers REG[
0
] through REG[
31
] and all 32 half adders HA[
0
] through HA[
31
] are activated during each cycle of the 1 Hz. clock. It is also obvious that the vast majority of the values stored in the bit registers REG[
0
] through REG[
31
]will not change during any given clock cycle. For example, the value in the bit register REG[
15
] will change only once in 2{circle around ( )}15 seconds or about once in 9 hours even though the same bit register REG[
15
] is activated for a possible change once every second of those 9 hours. The value of the bit register REG [
31
] remains unchanged until 2{circle around ( )}31 seconds have elapsed, or approximately 68 years.
Power consumption is a critical factor in the design and use of electronic devices. Many embedded systems run off a limited power supply, such as a battery. Unlike the bus clock that shuts off during a power down, the real time clock continues to operate and to draw power. Continuous power consumption by the real time clock shortens the amount of time available between battery recharging or replacement. Even embedded systems that draw power from an outside source can reduce costs by reducing the power consumption of the always-running real time clock.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a real time clock with a power saving counter for an embedded system.
Briefly summarized, the claimed invention discloses a source of an oscillating timing signal and a serially connected plurality of register units, each register unit having a bit register for storing clock data, a half adder for incrementing the clock data stored in the bit register, and an activation circuit for activating the bit register.
Each bit register includes a first input for receiving an activation signal, a second input for receiving data to be stored within the register, and a first output for outputting the value of the stored data to the corresponding half adder.
Each half adder includes a first input for receiving a first value and a second input for receiving the data stored in the corresponding bit register. In normal practice, the first value is a binary carry term from the previous half adder but it could be any value. Each half adder also includes a first output for outputting a binary sum term to the second input of the bit register and a second output for outputting the binary carry term.
Each activation circuit includes a first input for receiving the oscillating timing signal and a second input for receiving the first value. Again, norm

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