Semiconductor device

Details Semiconductor device Semiconductor device

2003-01-30

2004-11-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S329000, C257S330000, C257S331000, C257S339000, C257S340000, C438S270000

Reexamination Certificate

active

06825565

ABSTRACT:

BACKGROUND
There exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the vertical semiconductor device, which includes electrodes distributed on both major surfaces of the semiconductor chip and a vertical drift region, which makes a current flow in the thickness direction of the semiconductor chip. To reduce the tradeoff relation, the vertical drift region has been provided with an alternating conductivity type structure formed of heavily doped vertical n-type regions and heavily doped vertical p-type regions laminated alternately along the major surfaces of the semiconductor chip. The vertical drift region having the alternating conductivity type structure is depleted quickly. In the peripheral region of the semiconductor device, in which substantially no current flows, depletion layers hardly expand outward or into the deep portion of the semiconductor substrate, since the vertical n-type regions and the vertical p-type regions constituting the alternating conductivity type structure in the peripheral region are doped heavily. Due to the heavily doped vertical ntype regions and the heavily doped vertical p-type regions, the electric field strength in the peripheral region soon reaches the critical value for silicon before the applied voltage reaches the designed breakdown voltage of the device. Therefore, the designed breakdown voltage is not obtained.
For obviating the problem described above, it is preferable to provide the peripheral region with an alternating conductivity type structure doped more lightly than the alternating conductivity type structure in the drift region. Alternatively, it is preferable to provide the peripheral region with an alternating conductivity type structure including vertical n-type regions and vertical p-type regions alternately arranged at a pitch of repeating narrower than the pitch of repeating in the drift region.
FIG. 30
is a top plan view of a conventional vertical MOSFET showing the drift region and the peripheral region (breakdown withstanding region) thereof.
FIG. 31
is a vertical cross section taken along line
31
—
31
of FIG.
30
.
FIG. 32
is a vertical cross section taken along line
32
—
32
of FIG.
30
. Referring now to these figures, the n-channel vertical MOSFET includes an n
+
-type drain layer (contact layer)
11
with low electrical resistance, a drain electrode
18
on the back surface (second major surface) of the semiconductor chip and in electrical contact with n
+
-type drain layer
11
, a drift region
22
including a first alternating conductivity type layer formed on n
+
-type drain layer
11
, heavily doped p-type base regions (p-type well regions or channel diffusion regions)
13
a
formed selectively in the surface portion of the drift region
22
, a heavily doped n
+
-type source region
14
formed selectively in the surface portion of the p-type base region
13
a
, a polysilicon gate electrode layer
16
above the first major surface of the semiconductor chip with a gate insulation film
15
interposed therebetween, and a source electrode
17
in electrical contact with the p-type base regions
13
a
and the n
+
-type source regions
14
via contact holes bored through an interlayer insulation film
19
a
. The n
+
-type source region
14
is formed shallowly in the p-type base region
13
a
shaped with a well such that a double-diffusion MOS region constituting the active region of the device is formed. A p
+
-type contact region
26
is in the p-type base region
13
a
. Although not shown in the figures, a gate electrode layer
16
is connected to a gate wiring metal film above the gate electrode layer
16
.
The first alternating conductivity type layer in drift region
22
includes first n-type regions
22
a
and first p-type regions
22
b
. The first n-type regions
22
a
and the first p-type regions
22
b
are shaped with respective layers extending vertically in the thickness direction of the semiconductor chip. The first n-type regions
22
a
and the first p-type regions
22
b
are laminated alternately along the major surface of the semiconductor chip. The first n-type regions
22
a
, with the upper ends thereof are in contact with the sandwiched regions
12
e
between the p-type base regions
13
a
, provide a substantial current path in the on-state of the device. The lower ends of the first n-type regions
22
a
are in contact with the n
+
-type drain layer
11
. The upper ends of the first p-type regions
22
b
are in contact with the well bottoms of the respective p-type base regions
13
a
. The lower ends of the first p-type regions
22
b
are in contact with the n
+
-type drain layer
11
.
The n-channel vertical MOSFET includes also a peripheral region
20
between the surface of the semiconductor chip and the n
+
-type drain layer
11
and surrounding the drift region
22
. The peripheral region
20
includes a second alternating conductivity type layer, including second n-type regions
20
a
and second p-type regions
20
b
. The second n-type regions
20
a
and the second p-type regions
20
b
are shaped with respective layers extending vertically in the thickness direction of the semiconductor chip. The second n-type regions
20
a
and the second p-type regions
20
b
are laminated alternately along the major surface of the semiconductor chip. An oxide film (insulation film)
23
made of a thermal oxide or a phosphorus silica glass (PSG) is formed on the second alternating conductivity type layer in the peripheral region
20
for surface protection and for surface stabilization. To facilitate expanding depletion layers in the second alternating conductivity type layer, the second alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer. Alternatively, the second pitch of repeating P
2
, namely where a pair of the second n-type region
20
a
and the second p-type region
20
b
repeat, is narrower than the first pitch of repeating P
1
, namely where a pair of the first n-type region
22
a
and the first p-type region
22
b
repeat.
The vertical MOSFET shown in
FIGS. 30 through 32
has the following problems. Since the outermost first n-type region
22
aa
of the first alternating conductivity type layer in the drift region
22
is in contact with the innermost p-type region
20
bb
of the second alternating conductivity type layer, the impurity concentration therein are different from the impurity concentration in the first alternating conductivity type layer or the pitch of repeating thereof is different from the pitch of repeating in the first alternating conductivity type layer, causing charge imbalance between the outermost first n-type region
22
aa
and the innermost p-type region
20
bb
. Since none of the outermost first n-type region
22
aa
and the innermost p-type region
20
bb
is depleted completely in the off-state of the device, electric field localization is formed in the boundary plane X between the first and second alternating conductivity type layers. Therefore, it is difficult to obtain the designed breakdown voltage. Since the charge imbalance between the outermost first n-type region
22
aa
and the innermost p-type region
20
bb
causes larger lowering of the breakdown voltage as the alternating conductivity type layers are designed to be thicker for obtaining a vertical semiconductor device of a higher breakdown voltage class, the alternating conductivity type layer formed in the peripheral region of the device for obtaining a higher breakdown voltage does not work as intended.
Accordingly, there is a need for a semiconductor device, including a drift region formed of an alternating conductivity type layer and a peripheral region formed of an alternating conductivity type layer, which facilitates relaxing the surface electric field mainly in the peripheral region so that a higher breakdown voltage and a higher current capacity may be realized. The present invention addresses this need.
SUMMARY OF THE INVENTION
The p

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