Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2002-08-20
2004-06-15
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000, C377S047000
Reexamination Certificate
active
06750686
ABSTRACT:
The present invention concerns frequency dividers, apparatus, and methods for frequency division. More particularly, this invention relates to a frequency divider architecture, circuit technique and method based on the zipper divider architecture.
Great efforts have been made in radio frequency (RF) design towards one-chip transceivers in standard complementary metal oxide semiconductor (CMOS) in recent years. Particularly the CMOS implementation of frequency dividers and frequency synthesizers—one of key building blocks in a transceiver—have attracted a lot of attention. The most notable trend here is the zipper divider architecture and the so called current-mode logic (CML).
The known zipper divider is comprised of a chain of divide-by-2/3 cells of identical circuitry.
Shown in
FIG. 1
is a conventional divide-by-2/3 cell
10
having five terminals
11
-
15
: clock input (CKin)
11
, divided clock output (CKout)
12
, mode control input (MDin)
13
, mode control output (MDout)
14
, and a programming input (P)
15
. Each divide-by-2/3 cell
10
consists of two circuit blocks: a prescaler logic block
16
which divides either by 2 or 3, controlled by a swallow signal (SW) generated by another block called end-of-cycle logic
17
.
When a programming bit P=0 (with MDin=1 or MDin=0) is applied at the programming input
15
, then the cell
10
divides by 2 and when P=1 and MDin=1 it divides by 3.
The divide-by-2/3 cells are typically implemented in CML. An elementary CML logic circuit comprises several stacked differential pairs, two resistive or active loads, and one tail current source. Depending on the input logic states, the tail current is so rerouted inside the CML logic circuit that the voltage drop over the two loads represent exactly the desired logic function. In such a circuit operation, the metal oxide semiconductor (MOS) transistors in each differential pair act simply as switches. The current consumption of the CML logic circuit is determined by the tail current, independent of the input frequency, and not affected whether an input signal is present or not.
An example of a known frequency divider
20
comprising a chain of six divide-by-2/3 cells
21
-
26
is depicted in FIG.
2
A. The divider
20
is capable of operating at an input clock frequency (CK
1
) in the GHz range.
FIG. 2B
shows the terminal signals of the frequency divider
20
. The clock input and clock output signals are depicted in the plots on the left hand side of FIG.
2
B and the mode control signals are depicted on the right hand side. The amplitudes of the clock input and clock output signals range in the present example between −500 mV and +500 mV (peak-to-peak) since the divider
20
is realized in CML. In the present example, for most of the time, the cells
21
-
26
divide their clock input by 2. If the division ratio is 3, the pulse width is wider, as visible on the left hand side of FIG.
2
B. In case of the signal CK
3
, for example, at the times t1 and t2 the division ratio is 3. This is due to the fact that a binary word P=111111 is applied to the programming input. If the programming inputs are always logic “1” the division ratio of the individual cells
21
-
26
is only determined by the mode control signal (MD) issued by a subsequent cell to a preceding cell.
As illustrated on the right hand side, these mode control signals (MD) are usually in a state
30
representing a logical “0” Only for a short period of time the mode control signals take on a state
31
representing a logical “1”. This is particularly true for the first few cells of a chain of cells.
Another frequency divider is described in the U.S. Pat. No. 5,581,214. This frequency divider, which is based on the traditional frequency divider architecture being different from the zipper divider architecture, can be switched off when not needed. Turning the frequency divider on and off limits its application strictly to time-division applications or the like. No power saving is being achieved if the frequency divider proposed in this US Patent is kept on. When the frequency divider circuit is alternately turned off, the power consumption is reduced but the divider ceases from working at the same time. The frequency divider is further characterized in that the complete prescaler logic is switched between on and off. The frequency divider is controlled by an external on/off signal. Estimates reveal that with the frequency divider proposed in the US Patent only a few percents of power can be saved.
Many systems and devices—such as mobile phones, personal digital assistants, palm tops, and so forth—have very limited power resources due to the fact that they rely on batteries.
Working at GHz frequency range and above, a frequency divider consumes unavoidably quite a lot of power, typically several mA. Power consumption of the frequency dividers is therefore an important performance parameter if one wants to employ them in systems and devices with limited resources.
It is therefore an object of the present invention to provide a frequency divider with much reduced power consumption and improved power efficiency.
A novel frequency divider architecture as well as a novel circuit technique and method are presented herein which allow to save power. The novel architecture and technique is based on the known zipper divider architecture in combination with current mode logic (CML).
The frequency divider architecture provided herein allows a power reduction of up to 50%, or even above. A preferable implementation of the inventive concept ensures correct logic operation all the time, i.e., no matter whether the tail currents are turned on or off.
According to the present invention only some of the subcircuits of the frequency divider are switched between on and off.
According to the invention proposed herein, the on-time is a fraction of one reference cycle.
The period of the on/off is fixed and is equal to that of the output frequency of the frequency divider.
According to the present invention, the on/off signal is generated by the frequency divider itself.
It is an advantage of the present invention that the frequency dividers remain operational irrespective of whether they are in an on-mode or an off-mode.
According to the present invention up to 50% power savings—and even more than 50%—can be achieved. The power efficiency is thus remarkably improved.
REFERENCES:
patent: 4184068 (1980-01-01), Washburn
patent: 4264863 (1981-04-01), Kojima
patent: 5065415 (1991-11-01), Yamashita
patent: 5581214 (1996-12-01), Iga
patent: 6066990 (2000-05-01), Genest
patent: 6281721 (2001-08-01), Kinget et al.
patent: 6593782 (2003-07-01), Pierschel et al.
Koninklijke Philips Electronics , N.V.
Nguyen Minh
Waxler Aaron
LandOfFree
Frequency divider with reduced power consumption, apparatus... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency divider with reduced power consumption, apparatus..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency divider with reduced power consumption, apparatus... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3362496