Method of driving a sustaining pulse for a plasma display...

Details Method of driving a sustaining pulse for a plasma display... Method of driving a sustaining pulse for a plasma display...

2000-01-10

2004-08-31

Lao, Lun-Yi (Department: 2673)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S063000, C345S208000

Reexamination Certificate

active

06784857

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of driving a sustaining pulse for a plasma display panel and a driver circuit for driving a plasma display panel, and more particularly to a method of driving a sustaining pulse for a plasma display panel to keep sustaining discharges in stable intensity for each display cell independently from variation in load to the display cells as well as a driver circuit for driving a plasma display panel to keep sustaining discharges in stable intensity for each display cell independently from variation in load to the display cells.
The plasma display panel is advantageous in possible reduction in thickness thereof, and also in its large contrast in display without substantial flicker as well as advantageous in possible enlargement of its screen The plasma display panel is further advantageous in high response speed and realizing a multi-color display by utilizing a fluorescent material due to self-emission type display. In recent years, the plasma display panel has been becoming to be used widely in various fields of displays for computers and color-displays.
FIG. 1
is a circuit diagram illustrative of a conventional circuit configuration of a driver circuit for driving a display cell of a plasma display panel. The driver circuit is connected to a display cell
16
. The driver circuit for driving the display cell
16
comprises an address driver
20
, a scanning driver
21
′ and a sustaining driver
22
′. The address driver
20
is connected through a data electrode
7
to the display cell
16
. The scanning driver
21
′ is also connected through a scanning electrode
3
to the display cell
16
. The sustaining driver
22
′ is also connected through a sustaining electrode
4
to the display cell
16
. The display cell
16
has a panel static capacitance between the scanning electrode
3
and the sustaining electrode
4
. The address driver
20
comprises a complementary MOS circuit which comprises a series connection of an n-channel MOS field effect transistor T
11
and a p-channel MOS field effect transistor T
10
between a ground line and a high voltage line Vd, wherein the high voltage line is connected to the p-channel MOS field effect transistor T
10
, whilst the ground line is connected to the n-channel MOS field effect transistor T
11
. The data electrode
7
is connected to an intermediate point between the p-channel MOS field effect transistor T
10
and the n-channel MOS field effect transistor T
11
.
The scanning driver
21
′ comprises seven diodes D
20
, D
21
, D
23
, D
31
, D
42
, D
52
and D
54
and five n-channel MOS field effect transistors T
21
, T
22
, T
23
, T
31
and T
42
as well as two p-channel MOS field effect transistors T
20
and T
52
. The scanning electrode
3
is connected to a first node N
1
of the scanning driver
21
′. The p-channel MOS field effect transistor T
20
is connected in series between the first node N
1
and a second node N
2
. The n-channel MOS field effect transistor T
21
is connected in series between the first node N
1
and a third node N
3
. The p-channel MOS field effect transistor T
20
and the n-channel MOS field effect transistor T
21
are connected in series between the second node N
2
and the third node N
3
, and the first node as the intermediate point between the p-channel MOS field effect transistor T
20
and the n-channel MOS field effect transistor T
21
is connected to the scanning electrode
3
. Two diodes D
20
and D
21
are connected in series between the second node N
2
and the third node N
3
in parallel to the series connection of the p-channel MOS field effect transistor T
20
and the n-channel MOS field effect transistor T
21
. The diode D
20
is connected between the first node N
1
and the second node N
2
in such a direction that the diode D
20
allows a current from the first node N
1
to the second node N
2
. The diode D
21
is connected between the first node N
1
and the third node N
3
in such a direction that the diode D
21
allows a current from the third node N
3
to the first node N
1
. The second node N
2
is connected to the sustaining driver
22
′. The third node N
3
is also connected to the sustaining driver
22
′. The diode D
23
and the n-channel MOS field effect transistor T
23
are connected in series between the second node N
2
and a voltage line Vbw which is applied with a voltage level Vbw. The diode D
23
is connected between the second node N
2
and the n-channel MOS field effect transistor T
23
in such a direction that the diode D
23
allows a current from the second node N
2
to the n-channel MOS field effect transistor
723
. The n-channel MOS field effect transistor T
23
connected between the diode D
23
and the voltage line Vbw. The diode D
31
and the n-channel MOS field effect transistor T
31
are connected in series between the second node N
2
and a voltage line Vpe which is applied with a voltage level Vpe. The diode D
31
is connected between the second node N
2
and the n-channel MOS field effect transistor T
31
in such a direction that the diode D
31
allows a current from the second node N
2
to the n-channel MOS field effect transistor T
31
. The n-channel MOS field effect transistor T
31
connected between the diode D
31
and the voltage line Vpe. The diode D
42
and the n-channel MOS field effect transistor T
42
are connected in series between the second node N
2
and a voltage line Vs which is applied with a voltage level Vs. The diode D
42
is connected between the second node N
2
and the n-channel MOS field effect transistor T
42
in such a direction that the diode D
42
allows a current from the second node N
2
to the n-channel MOS field effect transistor T
42
. The n-channel MOS field effect transistor T
42
connected between the diode D
42
and the voltage line Vs. The diode D
54
and the n-channel MOS field effect transistor T
22
are connected in series between the third node N
3
and a voltage line Vw which is applied with a voltage level Vw. The diode D
54
is connected between the third node N
3
and the n-channel MOS field effect transistor T
22
in such a direction that the diode D
54
allows a current from the third node N
3
to the n-channel MOS field effect transistor T
22
. The n-channel MOS field effect transistor T
22
connected between the diode D
54
and the voltage line Vw. The diode D
52
and the p-channel MOS field effect transistor T
52
are connected in series between the third node N
3
and a ground line which is applied with a ground voltage level. The diode D
52
is connected between the third node N
3
and the p-channel MOS field effect transistor T
52
in such a direction that the diode D
52
allows a current from the p-channel MOS field effect transistor T
52
to the third node N
3
. The p-channel MOS field effect transistor T
52
connected between the diode D
52
and the ground line.
The sustaining driver
22
′ also comprises five diodes D
30
, D
40
, D
50
, D
60
and D
61
and four n-channel MOS field effect transistors T
30
and T
32
, T
60
and T
61
as well as a single p-channel MOS field effect transistor T
50
. A fourth node N
4
is connected to the sustaining electrode
4
. The diode D
30
and the n-channel MOS field effect transistor T
30
are connected in series between the fourth node N
4
and a voltage line Vp which is applied with a voltage level Vp. The diode D
30
is connected between the fourth node N
4
and the n-channel MOS field effect transistor T
30
in such a direction that the diode D
30
allows a current from the fourth node N
4
to the n-channel MOS field effect transistor T
30
. The n-channel MOS field effect transistor T
30
connected between the diode D
30
and the voltage line Vp. The diode D
40
and the n-channel MOS field effect transistor T
32
arc connected in series between the fourth node N
4
and a voltage line Vs which is applied with a voltage level Vs. The diode D
40
is connected between the fourth node N
4
and the n-channel MOS field effect transistor T
32
in such a di

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