Method for operating a non-volatile memory

Details Method for operating a non-volatile memory Method for operating a non-volatile memory

2003-03-12

2004-06-29

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185290

Reexamination Certificate

active

06757198

ABSTRACT:

BACKGROUNDING OF THE INVENTION
1. Field of Invention
The present invention relates to a method for operating a non-volatile memory (NVM). More particularly, the present invention relates to a method for operating an n-channel non-volatile memory.
2. Description of Related Art
A stacked gate memory has the property of permanently storing information that can be repeatedly read, written or erased. Moreover, the stacked gate memory also has the advantage of retaining information even when power is interrupted. Stacked gate memory is thus a type of non-volatile memory device that is widely used in personal computer and electronic systems.
A typical stacked gate memory comprises a doped polysilicon floating gate and a doped polysilicon control gate. The programming and the erasing of this type of stacked gate memory is accomplished by applying appropriate voltages to the source/drain regions and to the control gate; thereby causing electrons to inject into and to eject from the polysilicon floating gate.
In general, the common modes for the stacked gate memory to inject electron include the channel hot-electron injection and the Fowler-Nordheim tunneling. The programming or the erasing of the device depends on an injection or an ejection of electrons.
Additionally, a stacked gate memory device can further divide into a p-channel stacked gate memory device and an n-channel stacked gate memory device. Since the n-channel stacked gate memory device has a higher carrier mobility, a higher reading current and a faster reading speed are provided. Moreover, the programming of the n-channel stacked gate memory device is normally accomplished by the channel hot-electron injection while the erasing is accomplished by ejecting electrons to the source side by the Fowler-Nordheim tunneling effect.
Referring to
FIG. 1
,
FIG. 1
is simplified circuit diagram for a conventional n-channel stacked gate memory device array. A plurality of memory cells Q
m1
to Q
m4
, a plurality of bit lines BL1, BL2 and a plurality of word lines WL1, WL2 are shown in FIG.
1
. The drain regions of the memory cells Q
m1
and Q
m3
are coupled to the bit line BL1 and the drain regions of memory cells Q
m2
and Q
m4
are coupled to bit line BL2. The control gates of the memory cells Q
m1
and Q
m2
are coupled to the word line WL1, and the control gates of the memory cells Q
m3
and Q
m4
are coupled to the word line WL2. The source regions of the memory cells Q
m1
to Q
m4
share a common source line (SL).
Referring to Table 1 and
FIGS. 2A
to
2
B,
FIGS. 2A
to
2
B demonstrate the programming (FIG.
2
A), the reading and the erasing operations (
FIG. 2B
) of an n-channel stacked gate memory device. Table 1 summarizes the appropriate voltages that are applied for the various operations of the memory cell Q
m1
.
TABLE 1
Programming
Reading
Erasure
BL1
+V
d
1.0 V
Floating
BL2
0 V
  0 V
0 V
WL1
+V
cg
  V
cc
−V
cg
WL2
0 V
  0 V
0 V
SL
0 V
  0 V
+V
s
P-well
0 V
  0 V
0 V
As shown in Table 1,
FIGS. 2A and 2B
, 9 to 12 volts of bias V
cg
is applied to the word line WL1 (control gate
208
) and 5 to 7 volts of bias V
d
is applied to the bit line BL1 (drain region
202
) during the programming of the memory cell Q
m1
. The source line SL (source region
204
) and the P-well (or substrate)
200
are at 0 volt. Under such a bias condition, a large channel current (0.25~1 mamp/memory cell) is generated, and electrons then travel from the end of the source region
204
to the end of the drain region
202
. Hot electrons, which have sufficient momentum to overcome the energy barrier of the tunnel oxide layer, are generated when the electrons are accelerated by the high channel electric field at the end of the drain region
202
to generate hot electrons. Additionally, a high positive bias is applied to the control gate
208
causing the hot electrons to inject into the floating gate
206
from the drain region
202
as shown in FIG.
2
A. After the programming operation, the threshold voltage (V
T
) of the memory cell increases due to the residual negative charges in the floating gate
206
. These charges would remain in the floating gate
206
for a long period of time (for example, approximately for ten years at room temperature), unless they are removed intentionally.
As information is being read from the memory cell Q
m1
, a bias of V
d
volt is applied to the bit line BL1 (drain region
202
), a bias V
cc
is applied to the word line WL1 (control gate
206
), a bias of 0 volt is applied to the source line SL (source region
204
) and a bias of 0 volt is applied to the P-well. Since the channel of such a memory cell is closed and the current is low when electrons are present in the floating gate
206
, and the channel of the memory cell is opened and the current is high when electrons are absent in the floating gate, the logic “1” or the logic “0” stored in the memory cell is determined by the opening/closing of the channel and the size of the current flow.
To erase the memory cell Q
m1
, it is conventionally accomplished by the Fowler-Nordheim tunneling effect from the source side. A negative bias −V
cg
of about −8 volts to about −12 volts is applied to the word line WL1 (control gate
208
), a bias V
s
of about 4~6 volts is applied to the source line SL (source region
204
). Moreover, the bit line BL1 (drain region
202
) is floating while a bias of 0 volt is applied to the P-well
200
. Consequently, a great electric field is formed between the floating gate and a portion of the source region that is overlapped with the floating gate. Electrons are thus tunneled to the source region
204
from the floating gate
206
by the Fowler-Nordheim effect as shown in FIG.
2
B.
The programming of the above stacked gate memory device is based on the channel hot electron, wherein electrons are injected from the drain side. The effectiveness of electron injection is thereby very low. A higher voltage is thus required to provide a higher current during programming to improve the programming speed. A higher voltage, however, reduces the reliability of electronic devices and limits the size reduction of the device.
Moreover, based on the bias setups (WL1 as −V
cg
, SL as +V
s
) shown in FIG.
1
and table 1, when Q
m1
is erased, the memory cell Q
m2
is also erased. Therefore, when a stacked gate memory device is erased according to the prior art, a sector of memory cells is erased rather than a single memory cell. Many limitations are imposed on the programming and erasing of such a device. In other words, the conventional stacked gate memory device must perform the erasing and the coding actions to complete the writing of new information. Therefore, writing of new information requires a writing of all information every time (because it needs to erase the existing information first before any coding can be done). The operational speed for the writing operation of a stacked gate memory device is thus limited.
SUMMARY OF THE INVENTION
The present invention provides a method for operating a nonvolatile memory device, where the memory device can program or erase cell-by-cell, by byte, by sector and by block.
The present invention provides a method for operating a non-volatile memory device, wherein the current flow of the memory device is lowered to increase the operating speed of the memory device.
The present invention provides a method for operating a non-volatile memory device, wherein to program the memory cell by the channel FN tunneling effect, a positive voltage is applied to the control gate, a negative voltage is applied to the drain region, the source region is floating and a negative voltage is applied to the substrate. Moreover, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, the source region is floating and a positive voltage is applied to the substrate to erase the memory cell by the channel FN tunneling effect.
According to the present invention, the c

Affiliated with

Also associated with

Rating

Method for operating a non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for operating a non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for operating a non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3361577