Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2000-03-14
2004-08-17
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S123000, C205S149000, C205S157000
Reexamination Certificate
active
06776892
ABSTRACT:
TECHNICAL FIELD
The technical field of this invention is plating system electrodes used in the semiconductor plating industry for plating of metals such as copper onto semiconductor wafers and other semiconductor workpieces.
BACKGROUND OF THE INVENTION
In the production of semiconductor wafers and other semiconductor articles it is necessary to plate metals onto the semiconductor surface to provide conductive areas which transfer electrical current. There are two primary types of plating layers formed on the wafer or other workpiece. One is a blanket layer used to provide a metallic layer which covers large areas of the wafer. The other is a patterned layer which is discontinuous and provides various localized areas that form electrically conductive paths within the layer and to adjacent layers of the wafer or other device being formed.
The plating of copper onto semiconductor articles has proven to be a great technical challenge and at this time has not achieved commercial reality due to practical problems of forming copper layers on semiconductor devices in a reliable and cost efficient manner. This is caused in part by the relative difficulty in performing reactive ion etching or other selective removal of copper at reasonable production temperatures. The selective removal of copper is desirable to form patterned layers and provide electrically conductive interconnects between adjacent layers of the wafer or other workpiece.
Because reactive ion etching cannot be efficiently used, the industry has sought to overcome the problem of forming patterned layers of copper by using a damascene process where holes, more commonly called vias, trenches and other recesses are formed in the layer of semiconductor material in which the pattern of copper is desired. In the damascene processes the wafer is first provided with a metallic seed layer which is used to conduct electrical current during a subsequent metal electroplating step. The seed layer is a very thin layer of metal which can be laid down using several processes. The seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick. The seed layer can advantageously be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer is formed over a surface which is convoluted by the presence of vias, trenches, or other device features which are recessed. This convoluted nature of the exposed surface provides increased difficulties in forming the seed layer in a uniform manner. Nonuniformities in the seed layer can result in variations in the electrical current passing from the exposed surface of the wafer during the subsequent electroplating process. This in turn can lead to nonuniformities in the blanket layer electroplated onto the seed layer. Such nonuniformities can cause deformities and failures in the resulting semiconductor device being formed.
In the damascene processes, after the seed layer is laid down, then it is typical to plate additional metal onto the seed layer in the form of a blanket layer formed thereon. The blanket layer is typically electroplated and is used to fill the vias and trenches. The blanket layer is also typically plated to an extent which forms an overlying layer. Such a blanket layer will typically be formed in thicknesses on the order of 10,000-15,000 angstroms (1-1.5 microns).
The damascene processes also involve the removal of excess metal material present outside of the vias, trenches or other recesses. The metal is removed to provide a resulting patterned metal layer in the semiconductor device being formed. The excess plated material can be removed using chemical mechanical planarization. Chemical mechanical planarization is a processing step which uses the combined action of a chemical removal agent and an abrasive which remove and polish the exposed surface to remove undesired parts of the metal layer applied in the electroplating step.
The above process has been found very difficult to perform in a reliable and uniform manner when the electroplating process is performed using copper. Thus, the semiconductor industry has not as of this time been able to efficiently and economically produce semiconductor devices using copper metal as the principal conductive material of the device.
These challenges have in the past resulted in the use of aluminum and a variety of aluminum alloys as the metals of choice for forming metallized layers on semiconductor devices. Aluminum and its alloys have been acceptable because they can typically be removed in a defined and selective manner by reactive ion etch technology. This ion etch production technology uses a patterned photoresist layer which acts as a shield or stencil covering portions of an aluminum or alloy blanket layer which are to remain.
Despite the greater manufacturing ease, the performance of a semiconductor devices can be significantly enhanced by using copper since copper is significantly more conductive than aluminum. The frequent use of aluminum alloys further emphasizes the advantages of copper because the alloying introduces additional constituents to the matrix of the aluminum which further increases resistivity and decreases conductivity. Copper provides for more efficient and faster conduction of electrical signals within the semiconductor devices.
Thus, there has been a long-felt need in the art for improved semiconductor plating systems which can produce copper layers upon semiconductor articles which are uniform and can be produced in an efficient and cost-effective manner.
REFERENCES:
patent: 1308508 (1919-07-01), Roedel
patent: 3267010 (1966-08-01), Creutz et al.
patent: 3328273 (1967-06-01), Creutz et al.
patent: 3770598 (1973-11-01), Cruetz
patent: 3832291 (1974-08-01), Arcilesi et al.
patent: 4110176 (1978-08-01), Creutz et al.
patent: 4118301 (1978-10-01), Mayer et al.
patent: 4336114 (1982-06-01), Mayer et al.
patent: 4374709 (1983-02-01), Combs
patent: 5078852 (1992-01-01), Yee et al.
patent: 5167792 (1992-12-01), Kamitakahara et al.
patent: 5258047 (1993-11-01), Tokisue et al.
patent: 5312532 (1994-05-01), Andricacos et al.
patent: 5405518 (1995-04-01), Hsieh et al.
patent: 5522975 (1996-06-01), Andricacos et al.
patent: 5723028 (1998-03-01), Poris
Lowenheim, F.A., Electroplating, (1978), 12 pgs, McGraw-Hill Book Inc., New York.
Ritzdorf Thomas L.
Turner Jeffrey I.
Perkins Coie LLP
Semitool Inc.
Wong Edna
LandOfFree
Semiconductor plating system workpiece support having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor plating system workpiece support having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor plating system workpiece support having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3361375