Semiconductor device

Details Semiconductor device Semiconductor device

2003-03-13

2004-06-08

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S691000, C257S698000, C257S737000, C257S738000, C257S748000, C257S758000, C257S772000, C257S773000, C257S774000, C257S775000, C257S779000, C257S780000, C257S781000, C438S118000, C438S622000, C361S760000, C361S761000, C361S762000, C361S763000, C361S764000, C361S772000, C361S773000, C361S774000, C174S255000, C174S256000, C174S257000, C174S258000, C174S259000, C174S260000, C174S261000, C174S262000

Reexamination Certificate

active

06747356

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a technique effectively applied to the improvement of electric properties of a semiconductor device in which a multilayer circuit board is used.
There is, for example, a FC-BGA (Flip Chip-Ball Grid Array) as a chip for high-speed and multi-pin semiconductor. As a substrate for this package, a ceramic substrate and an organic substrate, etc. are used. The organic substrate is, however, more efficient in terms of the cost reduction. In order to deal with the multi-pin semiconductor chip, a build-up process, in which micro wirings are formed by the photolithography on the front and rear of a core layer having through holes formed by a drill, has recently been employed in the organic substrate.
In such a package for high-speed and multi-pin semiconductor chip, there are required good electric properties and, for example, is need for reducing a variation in the characteristic impedance values of all signal wirings in the package.
Note that a technique for solving noise problems without changing the characteristic impedance of the multilayer circuit board (wiring board) is disclosed in Japanese Patent Laid-open No. 2001-77541. The above technique is one for separating the signal wirings from a ground conductor layer in order to adjust the impedance relative to the ground conductor layer.
SUMMARY OF THE INVENTION
Meanwhile, Japanese Patent Laid-Open No. 2001-77541 discloses that the characteristic impedance changes depending on the thickness of an insulating layer arranged between the ground conductor layer and the signal wiring. However, it does not have any descriptions of the influence of the characteristic impedance, which is exerted on the signal wirings from a plurality of through-hole wirings formed on a core layer, the signal wirings being formed just above it via an insulating layer, in the case where a package board is, for example, a build-up board.
More specifically, in the actual package board, the plurality of through-hole wirings are formed in the core layer, and a large number of signal wirings are arranged also on the through-hole wirings via the insulating layer. Therefore, it is difficult to achieve the arrangement in which no signal wirings are formed above the through-hole wirings.
Accordingly, it is insufficient in the design of the package board to consider simply the change in the characteristic impedance depending on the thickness of the insulating layer arranged between the ground conductor layer and the signal wiring. Thereby, the problem occurs such that variation in impedances of the signal wirings on the through-hole wirings and the signal wirings on no through-hole wirings is beyond control.
An object of the present invention is to provide a semiconductor device capable of reducing the variation in the characteristic impedance of the wirings with high accuracy.
The above and other objects and novel characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
That is, the present invention comprises: a multilayer circuit board having an insulating base member, a first wiring layer arranged on a surface of the base member and provided with a power plane, a third wiring layer arranged on said first wiring layer via an insulating layer in a direction further away from said base member and provided with a power plane, and a second wiring layer arranged between said first and third wiring layers and provided with a signal wiring; and a semiconductor chip arranged on a main surface of said multilayer circuit board, wherein the gap between said first and second wiring layers is larger than that between said second and third wiring layers, and an area of the power plane of said third wiring layer is larger than that of the power plane of said first wiring layer.


REFERENCES:
patent: 4464704 (1984-08-01), Huie et al.
patent: 4931354 (1990-06-01), Wakino et al.
patent: 5347403 (1994-09-01), Uekusa
patent: 6376052 (2002-04-01), Asai et al.
patent: 6534723 (2003-03-01), Asai et al.
patent: 2001-77541 (1999-09-01), None

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