Integrated circuit device module

Details Integrated circuit device module Integrated circuit device module

1998-07-22

2004-08-31

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Smart card package

C257S775000, C257S723000, C257S678000, C257S784000, C257S685000, C257S531000, C257S692000, C361S760000, C361S777000, C361S788000, C361S767000, C361S768000, C361S737000, C361S784000, C361S101000, C361S102000

Reexamination Certificate

active

06784526

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device module on which a plurality of integrated circuit devices, such as memories, are mounted, and in particular to an innovative structure for preventing ringing on a signal line along which a signal is supplied in parallel to a plurality of integrated circuit devices.
2. Related Arts
Integrated circuit modules, such as semiconductor memory modules having large structures and a plurality of integrated circuit devices mounted on a single board, are frequently mounted on motherboards. With such an integrated circuit module, an address signal, a control signal and a common signal, such as a clock, are supplied along branched signal lines to the integrated circuit devices mounted on the board.
FIG. 1
is a plan view of an example semiconductor memory module showing part of the signal lines. A driver device
12
and nine semiconductor memory devices
14
to
30
are mounted on the surface of a motherboard
10
. Although not shown, nine other semiconductor memory devices are also mounted on the reverse face of the motherboard
10
. An external card-edge terminal
32
of the motherboard
10
is inserted into a connector on a main motherboard, not shown.
An address signal, for example, originates at an output terminal N
1
of the memory driver
12
and is supplied, along a common signal line
36
and along branch signal lines
38
and
40
on the obverse surface and branch signal lines
42
and
44
on the reverse surface which are connected at a node N
3
with the signal line
36
, to four groups of the
18
memory devices
14
to
30
. A dumping resistor R
1
is provided between the output terminal N
1
and the terminal N
2
of the common signal line
36
. Input terminals corresponding to the memory devices are connected to the branch signal lines
38
,
40
,
42
and
44
, which branch out in four directions at the node N
3
.
In the example shown in
FIG. 1
, a plurality of integrated circuit devices
14
to
30
, such as memory devices, are longitudinally mounted on the motherboard
10
. Nine other integrated circuit devices are mounted on the reverse face of the motherboard
10
at corresponding positions. Therefore, the driver device
12
is mounted longitudinally in the center portion, and a signal from the driver device
12
is transmitted along a signal supply line
36
and to a branch node N
3
, both of which are provided longitudinally in the center, and then to branched signal lines
38
,
40
,
42
and
44
which extend vertically in the longitudinal direction. With this arrangement, a signal is supplied to all the memory devices as symmetrically as possible.
The dumping resistor R
1
is provided while taking into account the reflection of signals at the farthest terminals N
4
, N
5
, N
6
and N
7
of the branched signal lines
38
,
40
,
42
and
44
. Specifically, the amplitude of a full-swing signal at the output terminal N
1
of the driver device
12
is reduced by half through the provision of the dumping resistor R
1
, and reflected signals are superimposed on each other at the terminals N
4
to N
7
for the branched signal lines
38
to
44
. Finally, the potential of the branched signal lines becomes a full-swing potential. That is, the signal passes through the output terminal N
1
, the node N
2
and the branch node N
3
and along the branched signal lines
38
to
44
. The signals are reflected at the terminals N
4
to N
7
on the branched signal lines, and the reflected signals are returned via the respective branched signal lines to the node N
3
.
However, as is apparent from
FIG. 1
, the lengths of the branched signal lines
38
to
44
are not always equal. This is because, since the mounting direction for the integrated circuit devices
14
to
30
, such as memory devices, on the motherboard
10
is the same, the positional relationship between their corresponding external terminals is reversed at upper and lower locations on the motherboard, as is shown in FIG.
1
. As a result, on the obverse surface of the motherboard
10
, for example, the distance from the node N
3
to the terminal N
4
is not the same as the distance from the node N
3
to the terminal N
5
, and thus there is a time lag (a skew) between signals reaching integrated circuit devices positioned at their edges. A signal which reaches an edge is reflected, and the reflected signal is transmitted to the opposite terminal N
4
or N
5
. Therefore, it has been found that, since a skewed reflected signal is superimposed on an original signal, and reflected signals having a phase difference interfere with each other, a vibrating waveform called ringing occurs.
FIG. 2
is a graph showing a signal waveform for a simulation at the nodes N
1
to N
5
of the module in FIG.
1
.
FIG. 3
is a graph showing a signal waveform when the first 4 nsec period in
FIG. 2
is enlarged along the time axis. As is shown by the signal waveform in
FIG. 2
, a pulse signal having an amplitude of 3 V rises and falls within a short time period at the output terminal N
1
of the device driver
12
. At the node N
2
, due to the dumping resistor R
1
, the inclination of the rise of a signal is ½.
Because of the existence of a dumping resistor R
2
, a signal at the node N
2
rises to an amplitude of 1.5 V at an inclination which is half that for the rise of the signal at the output terminal N
1
. Since the module in
FIG. 1
is so designed that the rising time is shorter than the reciprocal transmission time for a supplied signal, the potential at the node N
2
is temporarily maintained at 1.5 V. Then, when the signal reflected at the node N
4
or N
5
is superimposed on the original signal, the potential at the node N
2
is raised to 3 V. Similarly, a signal at the output terminal N
1
falls at 3 V, whereas a signal at the node N
2
first falls to 1.5 V, due to the dumping resistor R
1
, and then to 0 V, due to the superimposing of the signals reflected at the nodes N
4
and N
5
.
Since the distance between the branch node N
3
and the node N
4
is shorter than the distance between the branch node N
3
and the node N
5
, first a signal at the node N
4
rises, and then, after being slightly skewed, a signal at the node N
5
rises. Since the signal reflected at the node N
4
or N
5
is superimposed on the original signal, the resultant signal does not have a step shaped waveform, as is shown for the node N
2
, and substantially rises and falls at the same inclination as that for the output terminal N
1
.
However, since the reflected signals interfere with each other due to skewing of signals at the nodes N
4
and N
5
, ringing in the signals at the nodes N
4
and N
5
occurs, as is shown in the graphs. Such ringing causes the vibration of signals input to the memory devices
30
(I) and
14
(A) at the nodes N
4
and N
5
, respectively, and also causes an erroneous operation to be performed.
Such input signal vibration occurs not only with address signals, but also with control signals and clock signals which are supplied in common by the driver device
12
. In other words, for a module on which a plurality of logic devices are mounted, the same vibration problem occurs with a control signal and a clock signal which are used in common.
SUMMARY OF THE INVENTION
To resolve the above problem, it is one objective of the present invention to provide an integrated circuit device module for eliminating vibration, which accompanies a difference in the lengths of branched signal lines, of signals which are input to integrated circuit devices located at the distal ends of branched signal lines.
It is another objective of the present invention to provide an integrated circuit device module which resolves a problem concerning interference occurring between reflected signals at the distal ends of branched signal lines.
It is an additional objective of the present invention to provide an integrated circuit device module wherein signal skewing at the distal ends of branched signal lines is eliminated.
It is a further ob

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